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ST
Sitronix
1. Introduction
ST7712
262K Color Single-Chip TFT Controller/Driver
The ST7712 is a single-chip which generates 396 Source lines and 132 gate lines controller/driver for 262K color TFT dot graphic display. ST7712 support 18-bit high-speed bus interface and Serial Peripheral Interface (SPI), thus it can perform bi-operation functions, data transfer, and high-speed RAM write function. Display data can be stored in an on-chip display data RAM of 132x396x6 bits. It can perform display data RAM read/write operation without external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. Features
Driver Output Circuits
-396 source output -132 gate output
On-chip Low Power Analog Circuit
-On-chip oscillator circuit -Voltage converter generating liquid crystal driver up to 6-time scale -Simultaneous availability of 262K color with -correction function
On-chip Display Data RAM
-Capacity: 396 x 132 x 6 =313,632bits -65K colors (RGB)= (565) mode -262K colors (RGB)= (666) mode
Operating Voltage Range
-Vcc: 2.4~3.3V (logic power supply) -Vci: 2.5~3.3V (analog power supply) -IOVcc: 1.8~3.3V (interface power supply) -Source line voltage: DDVDH=4.5~6.0V
Applicable Duty Ratios
- Various partial display - Partial window moving & data scrolling
Microprocessor Interface
-8/9/16/18-bit parallel bi-directional interface with -6800-series or 8080-series -4-line serial interface -3-line serial interface
Package Type
-Application for COG
ST7712
6800 , 8080 ,4-Line , 3-Line interface
Ver 2.2
1/113
2006/07/07
ST7712
3. Pad Arrangement
Chip size (um): 15,800x1,380 PAD coordinate: PAD center Coordinate origin: Chip center Chip thickness (um): 40025 Bump height (um):152
Pad Arrangement (Unit: um): Pad No. 1~ Pad No. 534: 26 x 86
26 30 26
86 116 30 86
28
28
Pad No. 535~ Pad No. 692: 66 x 76
66 25 (min.) 66
76
95 (min.)
Alignment Mark (Unit: um):
Ver 2.3
2/113
2007/07/19
ST7712
4. Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Ver 2.3 PIN Name DUMMYA G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 X 7710 7620.5 7592.5 7564.5 7536.5 7508.5 7480.5 7452.5 7424.5 7396.5 7368.5 7340.5 7312.5 7284.5 7256.5 7228.5 7200.5 7172.5 7144.5 7116.5 7088.5 7060.5 7032.5 7004.5 6976.5 6948.5 6920.5 6892.5 6864.5 6836.5 6808.5 6780.5 6752.5 6724.5 6696.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 PAD No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 3/113 PIN Name G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 X 6668.5 6640.5 6612.5 6584.5 6556.5 6528.5 6500.5 6472.5 6444.5 6416.5 6388.5 6360.5 6332.5 6304.5 6276.5 6248.5 6220.5 6192.5 6164.5 6136.5 6108.5 6080.5 6052.5 6024.5 5996.5 5968.5 5940.5 5912.5 5884.5 5856.5 5828.5 5800.5 Y 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 570.715 570.715 454.715 2007/07/19
VCMDUMMY1 5726.5 DUMMYB S395 5631.5 5557.5
ST7712
PAD No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 PIN Name S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 X 5529.5 5501.5 5473.5 5445.5 5417.5 5389.5 5361.5 5333.5 5305.5 5277.5 5249.5 5221.5 5193.5 5165.5 5137.5 5109.5 5081.5 5053.5 5025.5 4997.5 4969.5 4941.5 4913.5 4885.5 4857.5 4829.5 4801.5 4773.5 4745.5 4717.5 4689.5 4661.5 4633.5 4605.5 4577.5 4549.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 PAD No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 PIN Name S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 X 4521.5 4493.5 4465.5 4437.5 4409.5 4381.5 4353.5 4325.5 4297.5 4269.5 4241.5 4213.5 4185.5 4157.5 4129.5 4101.5 4073.5 4045.5 4017.5 3989.5 3961.5 3933.5 3905.5 3877.5 3849.5 3821.5 3793.5 3765.5 3737.5 3709.5 3681.5 3653.5 3625.5 3597.5 3569.5 3541.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715
Ver 2.3
4/113
2007/07/19
ST7712
PAD No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 PIN Name S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 X 3513.5 3485.5 3457.5 3429.5 3401.5 3373.5 3345.5 3317.5 3289.5 3261.5 3233.5 3205.5 3177.5 3149.5 3121.5 3093.5 3065.5 3037.5 3009.5 2981.5 2953.5 2925.5 2897.5 2869.5 2841.5 2813.5 2785.5 2757.5 2729.5 2701.5 2673.5 2645.5 2617.5 2589.5 2561.5 2533.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 PAD No. 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 PIN Name S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 X 2505.5 2477.5 2449.5 2421.5 2393.5 2365.5 2337.5 2309.5 2281.5 2253.5 2225.5 2197.5 2169.5 2141.5 2113.5 2085.5 2057.5 2029.5 2001.5 1973.5 1945.5 1917.5 1889.5 1861.5 1833.5 1805.5 1777.5 1749.5 1721.5 1693.5 1665.5 1637.5 1609.5 1581.5 1553.5 1525.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715
Ver 2.3
5/113
2007/07/19
ST7712
PAD No. 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 PIN Name S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 X 1497.5 1469.5 1441.5 1413.5 1385.5 1357.5 1329.5 1301.5 1273.5 1245.5 1217.5 1189.5 1161.5 1133.5 1105.5 1077.5 1049.5 1021.5 993.5 965.5 937.5 909.5 881.5 853.5 825.5 797.5 769.5 741.5 713.5 685.5 657.5 629.5 601.5 573.5 545.5 517.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 PIN Name S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 X 489.5 461.5 433.5 405.5 377.5 349.5 321.5 293.5 265.5 237.5 209.5 181.5 153.5 125.5 97.5 69.5 41.5 -41.5 -69.5 -97.5 -125.5 -153.5 -181.5 -209.5 -237.5 -265.5 -293.5 -321.5 -349.5 -377.5 -405.5 -433.5 -461.5 -489.5 -517.5 -545.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715
Ver 2.3
6/113
2007/07/19
ST7712
PAD No. 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 PIN Name S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 X -573.5 -601.5 -629.5 -657.5 -685.5 -713.5 -741.5 -769.5 -797.5 -825.5 -853.5 -881.5 -909.5 -937.5 -965.5 -993.5 -1021.5 -1049.5 -1077.5 -1105.5 -1133.5 -1161.5 -1189.5 -1217.5 -1245.5 -1273.5 -1301.5 -1329.5 -1357.5 -1385.5 -1413.5 -1441.5 -1469.5 -1497.5 -1525.5 -1553.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 PAD No. 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 PIN Name S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 X -1581.5 -1609.5 -1637.5 -1665.5 -1693.5 -1721.5 -1749.5 -1777.5 -1805.5 -1833.5 -1861.5 -1889.5 -1917.5 -1945.5 -1973.5 -2001.5 -2029.5 -2057.5 -2085.5 -2113.5 -2141.5 -2169.5 -2197.5 -2225.5 -2253.5 -2281.5 -2309.5 -2337.5 -2365.5 -2393.5 -2421.5 -2449.5 -2477.5 -2505.5 -2533.5 -2561.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715
Ver 2.3
7/113
2007/07/19
ST7712
PAD No. 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 PIN Name S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 X -2589.5 -2617.5 -2645.5 -2673.5 -2701.5 -2729.5 -2757.5 -2785.5 -2813.5 -2841.5 -2869.5 -2897.5 -2925.5 -2953.5 -2981.5 -3009.5 -3037.5 -3065.5 -3093.5 -3121.5 -3149.5 -3177.5 -3205.5 -3233.5 -3261.5 -3289.5 -3317.5 -3345.5 -3373.5 -3401.5 -3429.5 -3457.5 -3485.5 -3513.5 -3541.5 -3569.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 PAD No. 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 PIN Name S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 X -3597.5 -3625.5 -3653.5 -3681.5 -3709.5 -3737.5 -3765.5 -3793.5 -3821.5 -3849.5 -3877.5 -3905.5 -3933.5 -3961.5 -3989.5 -4017.5 -4045.5 -4073.5 -4101.5 -4129.5 -4157.5 -4185.5 -4213.5 -4241.5 -4269.5 -4297.5 -4325.5 -4353.5 -4381.5 -4409.5 -4437.5 -4465.5 -4493.5 -4521.5 -4549.5 -4577.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715
Ver 2.3
8/113
2007/07/19
ST7712
PAD No. 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 PIN Name S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DUMMYC X -4605.5 -4633.5 -4661.5 -4689.5 -4717.5 -4745.5 -4773.5 -4801.5 -4829.5 -4857.5 -4885.5 -4913.5 -4941.5 -4969.5 -4997.5 -5025.5 -5053.5 -5081.5 -5109.5 -5137.5 -5165.5 -5193.5 -5221.5 -5249.5 -5277.5 -5305.5 -5333.5 -5361.5 -5389.5 -5417.5 -5445.5 -5473.5 -5501.5 -5529.5 -5557.5 -5631.5 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 570.715 PAD No. 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 PIN Name X Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 VCMDUMMY2 -5726.5 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 -5800.5 -5828.5 -5856.5 -5884.5 -5912.5 -5940.5 -5968.5 -5996.5 -6024.5 -6052.5 -6080.5 -6108.5 -6136.5 -6164.5 -6192.5 -6220.5 -6248.5 -6276.5 -6304.5 -6332.5 -6360.5 -6388.5 -6416.5 -6444.5 -6472.5 -6500.5 -6528.5 -6556.5 -6584.5 -6612.5 -6640.5 -6668.5 -6696.5 -6724.5 -6752.5
Ver 2.3
9/113
2007/07/19
ST7712
PAD No. 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 PIN Name G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 G0 DUMMYD DUMMY1 DUMMY2 DUMMY3 VCOM1 X -6780.5 -6808.5 -6836.5 -6864.5 -6892.5 -6920.5 -6948.5 -6976.5 -7004.5 -7032.5 -7060.5 -7088.5 -7116.5 -7144.5 -7172.5 -7200.5 -7228.5 -7256.5 -7284.5 -7312.5 -7340.5 -7368.5 -7396.5 -7424.5 -7452.5 -7480.5 -7508.5 -7536.5 -7564.5 -7592.5 -7620.5 -7710 -7710 -7609.15 -7508.3 -7408.33 Y 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 454.715 570.715 570.715 -583.465 -583.465 -583.465 -583.465 PAD No. 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 PIN Name VCOM1 DUMMY4 VGH VGH VLOUT2 C22+ C22+ C22C22C21+ C21+ C21C21C12+ C12+ C12+ C12+ C12C12C12C12VLOUT3 VGL VGL VGL VGL X Y -7313.33 -583.465 -7140 -7045 -6950 -6855 -6760 -6665 -6570 -6475 -6380 -6285 -6190 -6095 -6000 -5905 -5810 -5715 -5620 -5525 -5430 -5335 -5240 -5145 -5050 -4955 -4860 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465
IOVCCDUM1 -4715 IOVCCDUM1 -4620 IM0 IM1 IM2 IM3 -4525 -4430 -4335 -4240
IOGNDDUM1 -4145 IOGNDDUM1 -4050 FLM XCS -3955 -3860
Ver 2.3
10/113
2007/07/19
ST7712
PAD No. 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 PIN Name SCL SDI SDO RS RW_WR E_RD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 IOGNDDUM2 IOGNDDUM2 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 XRESET IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCI X -3765 -3670 -3575 -3480 -3385 -3290 -3195 -3100 -3005 -2910 -2815 -2720 -2625 -2530 -2435 -2340 -2245 -2150 -2055 -1960 -1865 -1770 -1675 -1580 -1485 -1390 -1295 -1200 -1105 -960 -865 -770 -675 -580 -485 -390 Y -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 PAD No. 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 PIN Name VCI VCI VCI VCI VCI VDDO VDDO VCILVL OSC1 OSC2 GND GND GND GND GND GND AGND AGND AGND AGND AGND AGND FUSA0 FUSA1 FUSA2 FUSA3 FUSA4 VSSF FUS0 FUS1 FUS2 FUS3 FUS4 REGP VGS VGS X -295 -200 -105 -10 85 180 275 370 495 590 715 810 905 1000 1095 1190 Y -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465
1298.775 -583.465 1393.775 -583.465 1502.415 -583.465 1597.415 -583.465 1692.415 -583.465 1787.415 -583.465 1896.055 -583.465 1996.055 -583.465 2096.055 -583.465 2196.055 -583.465 2296.055 -583.465 2396.055 -583.465 2496.055 -583.465 2596.055 -583.465 2696.055 -583.465 2796.055 -583.465 2896.055 -583.465 3025 3120 3215 -583.465 -583.465 -583.465
Ver 2.3
11/113
2007/07/19
ST7712
PAD No. 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 PIN Name VMON VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCIOUT VCIOUT VCIOUT VCIOUT DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VLOUT1 VLOUT1 C11C11C11C11C11+ X 3310 3405 3500 3595 3690 3785 3880 3975 4070 4165 4260 4355 4450 4545 4640 4735 4830 4925 5020 5115 5210 5305 5400 5495 Y -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 PAD No. 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 PIN Name C11+ C11+ C11+ VLPWR VCOMR VREG1OUT DUMMY5 VCOMH VCOMH VCOMH VCOML VCOML VCOML VLOUT4 VCL VCL DUMMY6 VCOM2 VCOM2 DUMMY7 DUMMY8 DUMMY9 X 5590 5685 5780 5875 5970 6065 6160 6255 6350 6445 6570 6665 6760 6855 6950 7045 7140 7313.33 7408.33 7508.3 7609.15 7710 Y -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465 -583.465
Ver 2.3
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ST7712
5. Block Diagram
S0 TO S395
G0 TO G131
VciLVL Vci VciOUT Vci1 VLOUT1
Voltage Adjustment Circuit
VGH,VGL
Source Drivers
Gate Drivers
DDVDH VLOUT2 VGH VLOUT3 VGL VLOUT4 VCL VREG1OUT VcomH VcomL Vcom
V0~V63 Step-up Ciruit Data Latches Gate Driver Outputs Controller Circuit RESET Oscillator Vcom Circuit Display Data RAM (DDRAM) [396X132X6] Timing Generator Display Address Counter Address Counter OSC1 OSC2
VGS
Gamma adjustment and Gray scale generator
Data Register Bus Holder
Instruction Register Instruction Decoder
MPU INTERFACE(PARALLEL & SERIAL)
IM3 IM2 IM1 IM0
RS XCS XRESET
SDO SDI
SCL
RW_WR
E_RD
D0 to D17
Ver 2.3
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6. Pin Function
6.1 Microprocessor Interface
Name IM0~IM3 I/O I Description Pins to select interface mode with MPU. IM3 0 0 0 0 0 0 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 IM1 0 0 1 1 0 0 0 0 1 1 IM0 0 1 0 1 0 1 0 1 0 1 Interface type 68-system 16 bits parallel 68-system 8 bits parallel 80-system 16 bits parallel 80-system 8 bits parallel 4-line SPI 3-line SPI 68-system 18 bits parallel 68-system 9 bits parallel 80-system 18 bits parallel 80-system 9 bits parallel Acceptable color mode 65K 65K 65K 65K 65K 65K 65K, 262K 65K, 262K 65K, 262K 65K, 262K 1 MCU No. 4 Connect Pin GND/ IOVcc
Select the ST7712. XCS I When XCS pin is set to "Low", ST7712 is selected and accessible. When XCS pin is set to "High", ST7712 is not selected and not accessible. Select register. RS I When RS pins is set to "Low": Register Index When RS pin is set to "High": Register value/Pixel Data Read/Write execution control pin. MPU Type E_RD Description Read / Write control input pin -RW = "H": When E is "H", D0 to D17 are in an output E_RD I 6800-series E state. -RW = "L": The data on D0 to D17 are latched at the falling edge of the E signal. Read enable clock input pin 8080-series /RD When /RD is "L", D0 to D17 are in an output state. In 3 lines and 4 lines-system bus interface is fixed to "L" Read/Write execution control pin MPU type RW_WR I 6800-series RW RW_WR Description Read / Write control input pin RW = "H" : read RW = "L" : write
MCU
1
MCU
1
MCU
Ver 2.3
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Write enable clock input pin 8080-series /WR The data on D0 to D17 are latched at the rising edge of the /WR signal. In 3 lines and 4 lines-system bus interface write data at the "L" level. In 3 lines and 4 lines-system bus interface read data at the "H" level. Reset pin. XRESET OSC1, I OSC2 18-bit parallel bi-directional data bus in 68-systemt/80-system bus interface mode. 8-bit bus: DB17-DB10 are used ,and DB9~DB0 are fixed to "H" or "L" 9-bit bus: DB17-DB9 are used ,and DB8~DB0 are fixed to "H" or "L" DB0~DB17 I/O 16-bit bus: DB17-DB10 and DB8-DB1 are used; DB9 and DB0 are fixed to "H" or "L" 18-bit bus: DB17-DB0 are all used. Synchronizing clock signal with amplitude IOVcc-GND in Serial Peripheral Interface SCL SDI SDO S0~S395 I (SPI). I O O Analog output signals to source of TFT. If not used, leave open-circuit. Gate line output signal. G0~G131 O High voltage output signals to gates of TFT. If not used, leave open-circuit. Frame head pulse with amplitude IOVcc-GND. Use when writing data to RAM in FLM Vcc, GND O synchronization with FLM. Logic-side Vcc: 2.4~3.3V. Logic-side GND: 0V Supply to interface pins, XREST, XCS, RW_WR, E_RD, RS, DB17-0. IOVcc=1.8V~3.3V. IOVcc must be supplied with the voltage in the same condition with IOVcc the internal logic voltage Vcc. When IOVcc=Vcc and assembled on COG, connect to Vcc on the FPC to avoid noise. 12 2 Power supply Power supply 1 MCU 132 Pins for serial data input (SDI). Input at the rising edge of SCL. Pins for serial data output (SDO). Output at the falling edge of SCL. Source line output signal. 1 MCU 18 MCU I When XRESET is "L", initialization is executed. Connect to an external resistor for R-C oscillation. 2 1 MCU or external RC circuit -
1
1 396
MCU MCU -
Ver 2.3
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6.2 Power Supply Pins
Name AGND Vci I/O I I Ground pin for analog. Power pins for analog circuit. Connect an external power supply of 2.5~3.3V. VciLVL I Generate a reference voltage (VciOUT, REGP) in accordance to the ratio set with VC2~0 registers from VciLVL level. Connect to the same power supply as the Vci, which has separate wiring from the VciLVL on the FPC. VciOUT O Internal reference voltage with amplitude Vci-GND. 4 Stabilizing capacitor, Vci1 VciOUT 1 Power supply Description No. 6 6 Connect Pin Power supply Power supply
Vci1 I/O
Reference voltage for the step-up circuit 2. Set Vci1 so that VLOUT2 and VLOUT3 do not exceed the pre-determined ranges.
6
VLOUT1
O
Output voltage from step-up circuit 1 . VLOUT1 = 4.0~5.5V
2
Stabilizing capacitor, DDVDH
DDVDH VLOUT2
I/O O
Power supply for TFT source driver. DDVDH=4.5V~6.0V Output voltage from step-up circuit 2. VLOUT2 = max 16.5V
6 1
VLOUT1 Stabilizing capacitor, VGH VLOUT2 Stabilizing capacitor, VGL VLOUT3 Stabilizing capacitor, VCL
VGH VLOUT3
I O
Power supply for TFT gate drive. VGH max. = 16.5V. Output voltage from step-up circuit 2. VLOUT3 = min -15V
2 1
VGL VLOUT4
I O
Power supply for TFT gate drive. VGL = min. - 15V. Output voltage from step-up circuit 4. VLOUT4 = 0 ~ -3.3V Power supply for VcomL drive. Connect to VLOUT4. VCL=0V~3.3V Step-up capacitor connection pins for step-up circuit 1. Step-up capacitor connection pins for step-up circuit 2 and circuit 4.
4 1
VCL C11+,C11C12+,C12C21+,C21C22+,C22-
I I/O
2 8 16
VLOUT4 Step-up capacitor Step-up capacitor
I/O
Output voltage generated from stepped-up of REGP voltage. VREG1OUT becomes (1) a source driver grayscale reference voltage VREG1OUT O VDH, (2) a VcomH level reference voltage, or (3) a Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH - 0.5)V. Vcom1 O A power supply for the TFT common electrode. Output an alternating
1
Step-up Capacitor
4
TFT
Ver 2.3
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Vcom2 current with amplitude VcomH-VcomL. The alternating cycle is changeable with register setting. The COM register controls the operation start/halt. This pin indicates a high level of Vcom generated in driving the Vcom VcomH O alternation. When the Vcom alternation is driven, this pin indicates a low level of VcomL O Vcom. An internal register can be used to adjust the voltage. Use to adjust VcomH with an external variable resistor. VcomR I To adjust VcomH, place a variable resistor between VREG1OUT and GND. VGS VMON VLPWR REGP VSSF FUS0~4 FUSA0~A4 VDDO IOVccDUM1 I --or open -----O interface or fixed pins . When not used, leave open. Internal GND level. Use to fix the electric potential for unused IOGNDDUM1,2 O interface or fixed pins. When not used, leave open. A power supply for the TFT common electrode. Output an alternating current with amplitude VcomH-VcomL. The alternating cycle is VCMDUMMY1,2 -changeable with register setting. The COM register controls the operation start/halt. DUMMYA,B,C,D DUMMY1,2,3,4,5,6,7,8,9 --DUMMY pad, When no used, leave open DUMMY pad, When no used, leave open 4 9 open open 2 Open 4 Open Test pin. Leave open. For Vcom voltage fine tune by trim fuse Test pin. Leave open. For Vcom voltage fine tune by trim fuse Test pin. Connect to capacitors externally Internal IOVcc level. Use to fix the electric potential for unused 1 1 5 4 2 2 Open Open Open Open Capacitor or open Open A reference level for the grayscale voltage generating circuit. Test pin. Leave open. Test pin. Connect to capacitors externally or leave open. 2 1 1 GND Open Capacitor 1 Variable resistor or open 3 3 Stabilizing Capacitor Stabilizing Capacitor command electrode
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7. Functional Description
7.1 Microprocessor Interface
Chip Select Input
There is XCS pin for chip selection. The ST7712 can connect with MPU when XCS is "L". If XCS is "H", these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB17 are to be high impedance. And, in case of 4-line/3-line serial interface, the internal shift register and the counter are reset.
7.1.1 Selecting Parallel / Serial Interface
ST7712 has 10 types of interface with MPU, including two serial and eight parallel interfaces. This parallel or serial interface is determined by IM3~IM0 pins as shown in table 7.1.1.
Table 7.1.1 Parallel / Serial Interface Mode
Acceptable IM3 0 0 0 0 0 0 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 IM1 0 0 1 1 0 0 0 0 1 1 IM0 0 1 0 1 0 1 0 1 0 1 Interface type 68-series 16 bits parallel 68-series 8 bits parallel 80-series 16 bits parallel 80-series 8 bits parallel 4-line SPI 3-line SPI 68-series 18 bits parallel 68-series 9 bits parallel 80-series 18 bits parallel 80-series 9 bits parallel Data Bus Color mode DB17~DB10, DB8~DB1 DB17~DB10 DB17~DB10, DB8~DB1 DB17~DB10 SDI, SDO SDI, SDO DB17~DB0 DB17~DB9 DB17~DB0 DB17~DB9 65K 65K 65K 65K 65K 65K 65K, 262K 65K, 262K 65K, 262K 65K, 262K
7.1.2 8-bit/9-bit/16-bit/18-bit Parallel Interface
The ST7712 identifies various types of the data bus signals according to combinations of RS, E_RD and WR_RW. The signal types are shown as table 7.1.2.
Table 7.1.2 Parallel Data Transfer
Common RS H H L L E H H H H 68-system RW H L H L 80-system Description RD L H L H WR H L H L Display data read out Display data write Register status read Writes to internal register (instruction)
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7.1.2.1 Relation between Data Bus and Gradation Data
ST7712 offers the 65K color display, 262K color display. When using either 65K or 262K, you can specify color for each of R, G, B by using the palette function. Use the command ("Entry Mode (03H)" ID[1:0]) for switching between these modes.
(1) 65K color display 1. 8-bit mode D17 1 write 2 write
nd st
D16 R3 G1
D15 R2 G0
D14 R1 B4
D13 R0 B3
D12 G5 B2
D11 G4 B1
D10 G3 B0
D9 ---
D8 ---
D7 ---
D6 ---
D5 ---
D4 ---
D3 ---
D2 ---
D1 ---
D0 ---
R4 G2
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM. "--": Don't care 2 16-bit mode D17 write R4 D16 R3 D15 R2 D14 R1 D13 R0 D12 G5 D11 G4 D10 G3 D9 -D8 G2 D7 G1 D6 G0 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 --
Data is acquired through signal write operation and then written to the display RAM.
"--": Don't care
(2) 262K color display 1. 9-bit mode D17 1 write 2 write
nd st
D16 R4 G1
D15 R3 G0
D14 R2 B5
D13 R1 B4
D12 R0 B3
D11 G5 B2
D10 G4 B1
D9 G3 B0
D8 ---
D7 ---
D6
D5 ---
D4 ---
D3
D2 ---
D1 ---
D0 ---
R5 G2
---
---
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM. "--": Don't care 2. 18 bit mode D17 Write R5 D16 R4 D15 R3 D14 R2 D13 R1 D12 R0 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 D5 B5 D4 B4 D3 B3 D2 B2 D1 B1 D0 B0
Data is acquired through signal write operation and then written to the display RAM.
7.1.3 Serial Interface
The 4-line serial interface uses four pins XCS, SDI/SDO, SCL, and RS to enter commands and data. Meanwhile, the 3-line serial interface uses three pins XCS, SDI/SDO and SCL for the same purpose. Data read is not available in the serial interface. Data entered must be 8 bits in 4-line serial interface and 9 bits in 3-line serial interface. Refer to the following chart for entering commands, parameters or gray-scale data. The relation between gray-scale data and data bus in the serial input is the same as that in the parallel interface mode at every gradation.
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4-line SPI When entering data (parameters): RS= HIGH at the rising edge of the 8 SCL.
th
When entering instruction register: RS= LOW at the rising edge of the 8 SCL
th
3-line SPI When entering data (parameters): SDI= HIGH at the rising edge of the 1 SCL.
st
When entering instruction register: SDI= LOW at the rising edge of the 1 SCL.
st
If XCS is caused to HIGH before 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again.
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In order to avoid data transfer error due to incoming noise, it is recommended to set XCS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register. When executing the command RAMWR, set XCS to HIGH after writing the last address (after starting the 9 pulse in case of 9-bit serial input or after starting the 8 pulse in case of 8-bit serial input).
th th
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7-2 Access to DDRAM and Internal Registers
ST7712 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Fig. 7.2.1 and Fig 7.2.2 illustrates these relations.
Fig 7.2.1
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8080 series 16 bits/18 bits interface mode MPU signal Write Operation RS /WR DATA Internal signals /WR BUS HOLDER SOURCE ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Fig 7.2.2
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SPI 4-Line interface mode
SPI 3-Line interface mode
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7.3 Display Data RAM (DDRAM)
7.3.1 DDRAM
It is 396 X 132 X 6 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the gate address and source address. Since display data from MCU D8 to D0 and D17 to D9 correspond to one or two pixels of RGB, data transfer related restrictions are reduced, realizing the display flexing. MCU's read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration.
Memory Map (When using the 65Kcolor. 8-bit mode)
RGB alignment Column Pixels SS=0 Color Data
0 S0 S1 S2 S3 1 S4 S5 S393 131 S394 S395
R D17 D16 D15 D14 D13
Pixels SS=1 Color Data
G D12 D11 D10 D17 D16 D15 131
S394
B D14 D13 D12 D11 D10
R D17 D16 D15 D14 D13
G D12 D11 D10 D17 D16 D15 130
S391
B D14 D13 D12 D11 D10
R D17 D16 D15 D14 D13
G D12 D11 D10 D17 D16 D15 0
S1
B D14 D13 D12 D11 D10
S395
S393
S392
S390
S2
S0
R D17 D16 D15 D14 D13
GS=0
0 1 2 3 4 5 6 7 124 125 126 127 128 129 130 131
GS=1
131 130 129 128 127 126 125 124 7 6 5 4 3 2 1 0
G D12 D11 D10 D17 D16 D15
B D14 D13 D12 D11 D10
R D17 D16 D15 D14 D13
G D12 D11 D10 D17 D16 D15
B D14 D13 D12 D11 D10
R D17 D16 D15 D14 D13
G D12 D11 D10 D17 D16 D15
B D14 D13 D12 D11 D10
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Memory Map (When using the 65Kcolor. 16-bit mode)
Pixels SS=0 Color Data
0
S0 S1 S2
RGB alignment Column 1
S3 S4 S5 S393
131
S394 S395
R D17 D16 D15 D14 D13
Pixels SS=1 Color Data
G D12 D11 D10 D8 D7 D6 131
S394
B D5 D4 D3 D2 D1
R D17 D16 D15 D14 D13
G D12 D11 D10 D8 D7 D6 130
S391
B D5 D4 D3 D2 D1
R D17 D16 D15 D14 D13
G D12 D11 D10 D8 D7 D6 0
S1
B D5 D4 D3 D2 D1
S395
S393
S392
S390
S2
S0
R D17 D16 D15 D14 D13
GS=0
0 1 2 3 4 5 6 7 124 125 126 127 128 129 130 131
GS=1
131 130 129 128 127 126 125 124 7 6 5 4 3 2 1 0
G D12 D11 D10 D8 D7 D6
B D5 D4 D3 D2 D1
R D17 D16 D15 D14 D13
G D12 D11 D10 D8 D7 D6
B D5 D4 D3 D2 D1
R D17 D16 D15 D14 D13
G D12 D11 D10 D8 D7 D6
B D5 D4 D3 D2 D1
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Memory Map (When using the 262K color. 9-bit mode)
Pixels SS=0 Color Data
0
S0 S1 S2
RGB alignment Column 1
S3 S4 S5 S393
131
S394 S395
R D17 D16 D15 D14 D13 D12
S395
Pixels
G D11 D10 D9 D17 D16 D15 131
S394
B D14 D13 D12 D11 D10 D9
S393
R D17 D16 D15 D14 D13 D12
S392
G D11 D10 D9 D17 D16 D15 130
S391
B D14 D13 D12 D11 D10 D9
S390
R D17 D16 D15 D14 D13 D12
S2
G D11 D10 D9 D17 D16 D15 0
S1
B D14 D13 D12 D11 D10 D9
S0
SS=1 Color Data
GS=0
0 1 2 3 4 5 6 7 124 125 126 127 128 129 130 131
GS=1
131 130 129 128 127 126 125 124 7 6 5 4 3 2 1 0
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D17 D16 D15
B D14 D13 D12 D11 D10 D9
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D17 D16 D15
B D14 D13 D12 D11 D10 D9
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D17 D16 D15
B D14 D13 D12 D11 D10 D9
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Memory Map (When using the 262K color. 18-bit mode)
Pixels SS=0 Color Data
0
S0 S1 S2
RGB alignment Column 1
S3 S4 S5 S393
131
S394 S395
R D17 D16 D15 D14 D13 D12
S395
Pixels SS=1 Color Data
G D11 D10 D9 D8 D7 D6 131
S394
B D5 D4 D3 D2 D1 D0
S393
R D17 D16 D15 D14 D13 D12
S392
G D11 D10 D9 D8 D7 D6 130
S391
B D5 D4 D3 D2 D1 D0
S390
R D17 D16 D15 D14 D13 D12
S2
G D11 D10 D9 D8 D7 D6 0
S1
B D5 D4 D3 D2 D1 D0
S0
GS=0
0 1 2 3 4 5 6 7 124 125 126 127 128 129 130 131
GS=1
131 130 129 128 127 126 125 124 7 6 5 4 3 2 1 0
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D8 D7 D6
B D5 D4 D3 D2 D1 D0
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D8 D7 D6
B D5 D4 D3 D2 D1 D0
R D17 D16 D15 D14 D13 D12
G D11 D10 D9 D8 D7 D6
B D5 D4 D3 D2 D1 D0
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7.3.2 Gate Address Control Circuit
This circuit is used to control the address in the gate direction when MPU accesses the DDRAM or when reading the DDRAM to display image on the LCD. When the gate -direction scan is specified with RAM address command (21H) and the address are incremented from the start up to the end gate, the source address is incremented by 1 and the gate address returns to start page. The DDRAM supports up to 132 lines, and thus the total gate becomes 132. In the read operation, as the end gate is reached, the source address is automatically incremented by 1 and the gate address is returned to start gate. Using the address normal/inverse parameter of Driver output set(01H) command allows you to inverse the correspondence between the DDRAM address and command output.
7.3.3 Source Address Control Circuit
This circuit is used to control the address in the source direction when MPU accesses the DDRAM. You can specify a scope of the source address using source address set command. When the source -direction scan is specified with RAM address command (21H) and the address are incremented from the start up to the end gate, the gate address is incremented by 1 and the column address returns to start source. In the read operation, too, the gate address is automatically incremented by 1 and returned to start gate as the end source is reached. Just like the gate address control circuit, using the source address normal/inverse parameter of Driver output set(01H) command enables to inverse the correspondence between the DDRAM source address and segment output. This arrangement relaxes restrictions in the chip layout on the LCD module.
7.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MCU reads or writes the DDRAM. Since MCU's read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM white the LCD is turned on does not cause troubles such as flicking of the display images.
7.3.5 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the source line decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
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7.4 Partial Display
Using partial in command allows you turn on two separated partial display (division by line) of the screen. This mode requires less current consumption than the whole screen display, making it suitable for the equipment in the standby state.
Screen 1
: Display area (partial display area)
Screen 2
: Non-display area
If the partial display region is out of the Max. Display range, it would be no operation.
7.5 Area Scroll Display
Using the scroll volume set commands (VLE) allows you to scroll the display screen. You can select screen1 or screen2 to be scrolled with screen scroll enable set commands (VLE). Notice that you can not scroll two screens (screen1 and screen 2) at the same time. Please referred to command "Display control 1 (07H)" and Vertical Scroll Set (41H) for further description.
VLE=00
VLE=01
VLE=10
Stationary
Scrolled
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7-6 -Correction Function
The ST7712 incorporates -correction function to display 262K colors simultaneously by 8-level grayscale. The 8-level grayscale is determined by the by the gradient adjustment register and the micro-adjustment register. Select either positive or negative polarity of the registers according to the characteristics of a liquid crystal panel.
DDRAM
Display Data
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B5
B4
B3
B2
B1
B0
6
6
6
Positive Polarity Resigter
PKP02 PKP12 PKP22 PKP32 PKP42 PKP52 PRP02 PRP12 VRP02 VRP12 PKP01 PKP11 PKP21 PKP31 PKP41 PKP51 PRP01 PRP11 VRP01 VRP11 PKP00 PKP10 PKP20 PKP30 PKP40 PKP50 PRP00 PRP10 VRP00 VRP10
V0
VRP14
VRP03 VRP13
8
Grayscale 64 levels Amplifier
V63
64 grayscale Control
64 grayscale Control
64 grayscale Control
Negative Polarity Resigter
PKN02 PKN12 PKN22 PKN32 PKN42 PKN52 PRN02 PRN12 VRN02 VRN12 PKN01 PKN11 PKN21 PKN31 PKN41 PKN51 PRN01 PRN11 VRN01 VRN11 PKN00 PKN10 PKN20 PKN30 PKN40 PKN50 PRN00 PRN10 VRN00 vRN10
LCD Driver IC
VRN14
VRN03 VRN13
Display
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ST7712
7.6.1 Grayscale Amplifier
The eight levels (VIN0 t0 VIN7) of grayscale are determined by gradient adjustment register and the micro-adjustment register. The 8 levels are then divided into 64 levels (V0-63) by the ladder resistors placed between each level. (The structure of the grayscale amplifier is shown as below).
8 to 1 Selector 8 to 1 Selector 8 to 1 Selector 8 to 1 Selector 8 to 1 Selector 8 to 1 Selector
Grayscale Amplifier
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Structure of Ladder / 8 to 1 selector
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7.6.2 -Adjustment Register
The -adjustment registers set an appropriate grayscale voltage for the -characteristics of a liquid crystal display. The register group is categorized into the 4-types of register groups to adjust gradient and amplitude on the number of grayscale, the characteristics of the grayscale voltage. Each register can make an independent setting for the positive/negative polarity (the reference value and RGB are common for all registers). The figure below shows the operation of each adjusting register.
Grayscale Voltage
Grayscale Voltage
Grayscale Number
Grayscale Number
a. Gradient adjustment
Grayscale Voltage
b. Amplitude adjustment
Grayscale Voltage
Grayscale Number
Grayscale Number
c. Reference adjustment
d. Micro adjustment
The Operation of adjusting register
a) Gradient adjustment resistor The gradient adjustment resistors are used to adjust the gradient in the middle of the grayscale characteristics for the voltage without changing the dynamic range. It controls the variable resistor (VRHP (N) / VRLP (N)) of the ladder resistor for the grayscale voltage generator to achieve the adjustment. Also, there is a separate resistor on the positive and negative polarities in order for corresponding to asymmetry drive.
b) Amplitude adjustment resistor The Amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it controls the variable resistor (VRP(N)1) of the ladder resistor for the grayscale voltage generator located at lower side of the ladder resistor.
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c) Reference adjustment resistor The Reference-adjusting resistor is to adjust reference of the grayscale voltage. To accomplish the adjustment, it controls the variable resistor (VRP(N)0) of the ladder resistor for the grayscale voltage generator located at upper side of the ladder resistor.
d) Micro adjustment resistor The micro adjustment resistor is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors.
-correction registers
Register Gradient Adjustment Amplitude Adjustment Micro Adjustment Positive Polarity PRP0[2:0] PRP1[2:0] VRP0[3:0] VRP1[4:0] PKP0[2:0] PKP1[2:0] PKP3[2:0] PKP4[2:0] PKP5[2:0] PKP6[2:0] Negative Polarity PRN0[2:0] PRN1[2:0] VRN0[3:0] VRN1[4:0] PKN0[2:0] PKN1[2:0] PKN3[2:0] PKN4[2:0] PKN5[2:0] PKN6[2:0] Set-up contents Variable resistor VRHP(N) Variable resistor VRLP(N) Variable resistor VRP(N)0 Variable resistor VRP(N)1 The voltage of grayscale number 1 is selected by the 8 to 1 selector The voltage of grayscale number 8 is selected by the 8 to 1 selector The voltage of grayscale number 20 is selected by the 8 to 1 selector The voltage of grayscale number 43 is selected by the 8 to 1 selector The voltage of grayscale number 55 is selected by the 8 to 1 selector The voltage of grayscale number 62 is selected by the 8 to 1 selector
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7.6.3 Ladder resistors and 8 to 1 Selector
This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistance voltage. The variable and 8 to 1 resistors are controlled by the gamma resistor. Also, there are pins that connect to the external volume resistor and can compensate the variation among the panels.
Variable Resistors
There are 2 types of the variable resistors that is for the gradient adjustment (VRHP (N) / VRLP (N)) and for the oscillation adjustment (VRP (N)0/VRP (N)1). The resistance value is set by the gradient adjusting resistor and the oscillation adjustment resistor as below.
Gradient Adjustment (1) Register Value PRP(N)0 [2:0] 000 001 010 011 100 101 110 111 Resistance Value VRHP(N) 0R 4R 8R 12R 16R 20R 24R 28R
Gradient Adjustment (2) Register value PRP(N)1[2:0] 000 001 010 011 100 101 110 111 Resistance value VRLP(N) 0R 4R 8R 12R 16R 20R 24R 28R
Amplitude Adjustment (1) Register value VRP(N)[3:0] 0000 0001 0010 : : 1101 1110 1111 Resistance value VRP(N)0 0R 2R 4R : : 26R 28R 30R
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Oscillation Adjustment (2) Register value VRP(N)1[4:0] 00000 00001 00010 : : 11101 11110 11111 Resistance value VRP(N)1 0R 1R 2R : : 29R 30R 31R
8-to-1 Selector
In the 8-to-1 selector, the voltage level must be selected given by the ladder resistance and the micro-adjusting register and output the voltage the six types of the reference voltage, the VIN1 to VIN6. Following figure explains the relationship between the micro-adjusting register and the selecting voltage.
Relationship between Micro-adjustment Register and Selected Voltage
Register value PKP(N) [2:0]
VINP(N)1
KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8
VINP(N)2
KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16
Selected voltage VINP(N)3 VINP(N)4
KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32
VINP(N)5
KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40
VINP(N)6
KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48
000 001 010 011 100 101 110 111
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-Correction Voltage Formula (Positive polarity) --1
Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula VREG1OUT-V*VRP0/SUMRP VREG1OUT-V*(VRP0+5R)/SUMRP VREG1OUT-V*(VRP0+9R)/SUMRP VREG1OUT-V*(VRP0+13R)/SUMRP VREG1OUT-V*(VRP0+17R)/SUMRP VREG1OUT-V*(VRP0+21R)/SUMRP VREG1OUT-V*(VRP0+25R)/SUMRP VREG1OUT-V*(VRP0+29R)/SUMRP VREG1OUT-V*(VRP0+33R)/SUMRP VREG1OUT-V*(VRP0+33R+VRHP)/SUMRP VREG1OUT-V*(VRP0+34R+VRHP)/SUMRP VREG1OUT-V*(VRP0+35R+VRHP)/SUMRP VREG1OUT-V*(VRP0+36R+VRHP)/SUMRP VREG1OUT-V*(VRP0+37R+VRHP)/SUMRP VREG1OUT-V*(VRP0+38R+VRHP)/SUMRP VREG1OUT-V*(VRP0+39R+VRHP)/SUMRP VREG1OUT-V*(VRP0+40R+VRHP)/SUMRP VREG1OUT-V*(VRP0+45R+VRHP)/SUMRP VREG1OUT-V*(VRP0+46R+VRHP)/SUMRP VREG1OUT-V*(VRP0+47R+VRHP)/SUMRP VREG1OUT-V*(VRP0+48R+VRHP)/SUMRP VREG1OUT-V*(VRP0+49R+VRHP)/SUMRP VREG1OUT-V*(VRP0+50R+VRHP)/SUMRP VREG1OUT-V*(VRP0+51R+VRHP)/SUMRP VREG1OUT-V*(VRP0+52R+VRHP)/SUMRP VREG1OUT-V*(VRP0+68R+VRHP)/SUMRP VREG1OUT-V*(VRP0+69R+VRHP)/SUMRP VREG1OUT-V*(VRP0+70R+VRHP)/SUMRP VREG1OUT-V*(VRP0+71R+VRHP)/SUMRP VREG1OUT-V*(VRP0+72R+VRHP)/SUMRP VREG1OUT-V*(VRP0+73R+VRHP)/SUMRP VREG1OUT-V*(VRP0+74R+VRHP)/SUMRP VREG1OUT-V*(VRP0+75R+VRHP)/SUMRP VREG1OUT-V*(VRP0+80R+VRHP)/SUMRP VREG1OUT-V*(VRP0+81R+VRHP)/SUMRP VREG1OUT-V*(VRP0+82R+VRHP)/SUMRP VREG1OUT-V*(VRP0+83R+VRHP)/SUMRP VREG1OUT-V*(VRP0+84R+VRHP)/SUMRP VREG1OUT-V*(VRP0+85R+VRHP)/SUMRP VREG1OUT-V*(VRP0+86R+VRHP)/SUMRP VREG1OUT-V*(VRP0+87R+VRHP)/SUMRP VREG1OUT-V*(VRP0+87R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+91R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+95R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+99R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+103R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+107R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+111R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+115R+VRHP+VRLP)/SUMRP VREG1OUT-V*(VRP0+120R+VRHP+VRLP)/SUMRP Micro-adjusting register value -PKP02-00 ="000" PKP02-00="001" PKP02-00="010" PKP02-00="011" PKP02-00="100" PKP02-00="101" PKP02-00="110" PKP02-00="111" PKP12-10 ="000" PKP12-10 ="001" PKP12-10 ="010" PKP12-10 ="011" PKP12-10 ="100" PKP12-10 ="101" PKP12-10 ="110" PKP12-10 ="111" PKP22-10 ="000" PKP22-10 ="001" PKP22-20 ="010" PKP22-20 ="011" PKP22-20 ="100" PKP22-20 ="101" PKP22-20 ="110" PKP22-20 ="111" PKP32-30 ="000" PKP32-30 ="001" PKP32-30 ="010" PKP32-30 ="011" PKP32-30 ="100" PKP32-30 ="101" PKP32-30 ="110" PKP32-30 ="111" PKP42-40 ="000" PKP42-40 ="001" PKP42-40 ="010" PKP42-40 ="011" PKP42-40 ="100" PKP42-40 ="101" PKP42-40 ="110" PKP42-40 ="111" PKP52-50 ="000" PKP52-50 ="001" PKP52-50 ="010" PKP52-50 ="011" PKP52-50 ="100" PKP52-50 ="101" PKP52-50 ="110" PKP52-50 ="111" -Reference voltage VINP0 VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN
V: Potential difference between KV0 and KV49 = VREG1OUT*SUMRP*SUMRN / [SUMRP*SUMRN+EXVR*(SUMRP+SUMRN)]
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-Correction Voltage Formula (Positive polarity) --2
Voltage of grayscale V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VINP0 VINP1 V3+(V1-V3)*(8/24) V8+(V1-V8)*(450/800) V8+(V3-V8)*(16/24) V8+(V3-V8)*(12/24) V8+(V3-V8)*(8/24) V8+(V3-V8)*(4/24) VINP2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINP3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) Voltage of grayscale V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINP4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINP5 V60+(V55-V60)*(20/24) V60+(V55-V60)*(16/24) V60+(V55-V60)*(12/24) V60+(V55-V60)*(8/24) V62+(V55-V62)*(350/800) V62+(V60-V62)*(16/24) VINP6 VINP7
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-Correction Voltage Formula (Negative Polarity)--1
Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula VREG1OUT-V*VRN0/SUMRN VREG1OUT-V*(VRN0+5R)/SUMRN VREG1OUT-V*(VRN0+9R)/SUMRN VREG1OUT-V*(VRN0+13R)/SUMRN VREG1OUT-V*(VRN0+17R)/SUMRN VREG1OUT-V*(VRN0+21R)/SUMRN VREG1OUT-V*(VRN0+25R)/SUMRN VREG1OUT-V*(VRN0+29R)/SUMRN VREG1OUT-V*(VRN0+33R)/SUMRN VREG1OUT-V*(VRN0+33R+VRHP)/SUMRN VREG1OUT-V*(VRN0+34R+VRHP)/SUMRN VREG1OUT-V*(VRN0+35R+VRHP)/SUMRN VREG1OUT-V*(VRN0+36R+VRHP)/SUMRN VREG1OUT-V*(VRN0+37R+VRHP)/SUMRN VREG1OUT-V*(VRN0+38R+VRHP)/SUMRN VREG1OUT-V*(VRN0+39R+VRHP)/SUMRN VREG1OUT-V*(VRN0+40R+VRHP)/SUMRN VREG1OUT-V*(VRN0+45R+VRHP)/SUMRN VREG1OUT-V*(VRN0+46R+VRHP)/SUMRN VREG1OUT-V*(VRN0+47R+VRHP)/SUMRN VREG1OUT-V*(VRN0+48R+VRHP)/SUMRN VREG1OUT-V*(VRN0+49R+VRHP)/SUMRN VREG1OUT-V*(VRN0+50R+VRHP)/SUMRN VREG1OUT-V*(VRN0+51R+VRHP)/SUMRN VREG1OUT-V*(VRN0+52R+VRHP)/SUMRN VREG1OUT-V*(VRN0+68R+VRHP)/SUMRN VREG1OUT-V*(VRN0+69R+VRHP)/SUMRN VREG1OUT-V*(VRN0+70R+VRHP)/SUMRN VREG1OUT-V*(VRN0+71R+VRHP)/SUMRN VREG1OUT-V*(VRN0+72R+VRHP)/SUMRN VREG1OUT-V*(VRN0+73R+VRHP)/SUMRN VREG1OUT-V*(VRN0+74R+VRHP)/SUMRN VREG1OUT-V*(VRN0+75R+VRHP)/SUMRN VREG1OUT-V*(VRN0+80R+VRHP)/SUMRN VREG1OUT-V*(VRN0+81R+VRHP)/SUMRN VREG1OUT-V*(VRN0+82R+VRHP)/SUMRN VREG1OUT-V*(VRN0+83R+VRHP)/SUMRN VREG1OUT-V*(VRN0+84R+VRHP)/SUMRN VREG1OUT-V*(VRN0+85R+VRHP)/SUMRN VREG1OUT-V*(VRN0+86R+VRHP)/SUMRN VREG1OUT-V*(VRN0+87R+VRHP)/SUMRN VREG1OUT-V*(VRN0+87R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+91R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+95R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+99R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+103R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+107R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+111R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+115R+VRHP+VRLP)/SUMRN VREG1OUT-V*(VRN0+120R+VRHP+VRLP)/SUMRN Micro-adjusting register value -PKN02-00 ="000" PKN02-00="001" PKN02-00="010" PKN02-00="011" PKN02-00="100" PKN02-00="101" PKN02-00="110" PKN02-00="111" PKN12-10 ="000" PKN12-10 ="001" PKN12-10 ="010" PKN12-10 ="011" PKN12-10 ="100" PKN12-10 ="101" PKN12-10 ="110" PKN12-10 ="111" PKN22-10 ="000" PKN22-10 ="001" PKN22-20 ="010" PKN22-20 ="011" PKN22-20 ="100" PKN22-20 ="101" PKN22-20 ="110" PKN22-20 ="111" PKN32-30 ="000" PKN32-30 ="001" PKN32-30 ="010" PKN32-30 ="011" PKN32-30 ="100" PKN32-30 ="101" PKN32-30 ="110" PKN32-30 ="111" PKN42-40 ="000" PKN42-40 ="001" PKN42-40 ="010" PKN42-40 ="011" PKN42-40 ="100" PKN42-40 ="101" PKN42-40 ="110" PKN42-40 ="111" PKN52-50 ="000" PKN52-50 ="001" PKN52-50 ="010" PKN52-50 ="011" PKN52-50 ="100" PKN52-50 ="101" PKN52-50 ="110" PKN52-50 ="111" -Reference voltage VINN0 VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRN: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRN SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN
V: Potential difference between KV0 and KV49 = VREG1OUT*SUMRP*SUMRN / SUMRP*SUMRN+EXVR*(SUMRP+SUMRN)]
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Gamma Voltage Formula (Negative Polarity) --2
Voltage of grayscale V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VINN0 VINN1 V3+(V1-V3)*(8/24) V8+(V1-V8)*(450/800) V8+(V3-V8)*(16/24) V8+(V3-V8)*(12/24) V8+(V3-V8)*(8/24) V8+(V3-V8)*(4/24) VINN2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINN3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) Voltage of grayscale V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINN4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINN5 V60+(V55-V60)*(20/24) V60+(V55-V60)*(16/24) V60+(V55-V60)*(12/24) V60+(V55-V60)*(8/24) V62+(V55-V62)*(350/800) V62+(V60-V62)*(16/24) VINN6 VINN7
V0 Negative Polarity
Output Level
Positive Polarity V63 RAM data 111111
Relationship between RAM data and output voltage
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7.7 Oscillation circuit
The ST7712 can either use the internal resistor or external resistors to generate the oscillation.
7.7.1 Internal Resistor
The ST7712 can use the on-chip Oscillator without external resistor. When the internal oscillator is used, OSC1 and OSC2 must left open. This oscillator signal is used in the voltage converter and display timing generation circuit.
7.7.2 External Resistor
The ST7712 can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. If Rf is increased or power supply voltage is decrease, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section.
Notes: The Rf resistor value should be based on the RC loading of panel and FPC to fine tune Rf value to apparoach the osc frequency that customer need.
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7.8 Frame-Frequency Adjustment Function
The ST7712 includes frame frequency adjustment function. While the oscillation frequency is fixed, the frame frequency during the LC drive can be adjusted by the Frame cycle set instruction (0BH) setting (DIV, RTN). Setting the oscillation frequency high in advance allows switching the frame frequency in accordance to the kind of picture to display (i.e. moving/still picture). When displaying a still picture, set the frame frequency low to save power consumption, while setting the frame frequency high for displaying a moving picture which requires high-speed switching of screens.
7.8.1 Relationship between Liquid Crystal Drive Duty and Frame Frequency
The relationship between the liquid crystal drive duty and the frame frequency is calculated by the following formula. The frame frequency is adjusted through the Frame cycle set instruction (0BH) setting with the 1-H period adjustment bit (RTN bit) and the operation clock division bit (DIV bit).
Frame frequency =
fOSC Clock cycles per raster-row x division ratio x (Line+BP+FP)
[Hz]
fOSC: R-C oscillation frequency Line: Number of raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit The No. of raster-rows for the front porch: FP The No. of raster-row for hte back porch: BP
Example calculation
Number of drive raster-rows: 132 1-H period: 16 clock cycles (RTN3-0 = 0000) Operation clock division ratio: 1/1 fosc = 60 Hz x (0 + 16) clock x 1/1 x (132 + 16) lines = 142 (kHz) In this case, the R-C oscillation frequency becomes 142 kHz. Adjust the external resistor to the R-C oscillator to 142 kHz.
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7.9 Voltage Setting
VLOUT2 VGH(+9~16.5V)
BT
VLOUT1 DVDDH (4.5V~6.0V)
VREG1OUT
VCI(2.5~3.3V) VCC(2.4~3.3V) VREG1OUT(3.0V~DVDDH-0.5V) VCI1
VRH VDV
VCM/VCOMR
VcomH(3.0V~DVDDH-0.5V)
IOVCC(1.8~3.3V)
GND(0V)
BT VCOMG
VLOUT4
VcomL(VCL+0.5)~1V) VCL (0~-3.3V)
VLOUT3
VGL (-4V~-15V)
Note
1) the voltage will drop from the set voltage (an ideal voltage) with regard to each DDVDH, VGH, VGL, VCL output due to current consumption. (DDVDH - VREG1OUT) > 0.5V and (VcomL - VCL) > 0.5V show the relationship in relation to the actual voltage. When Vcom alternating frequency is high (e.g. alternation occurs by line), current consumption is also large. In this case, check voltage before use.
VGH
VDH VcomH Vcom Source Driver Output Gate Driver Output VGL VcomL
Voltage output to TFT LCD
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7.10 8-Color Display Mode
The ST7712 incorporates 8-color display mode. Using grayscale levels are V0 and V63 and all other level power supplies are halt. So that it's power consumption will be fewer. Also, during the 8-color mode, the Gamma micro adjustment register, PKP00-PKP52 and PKN00-PKN52 are invalid. Rewrite the data of DDRAM R/G/B to 000000 or 111111 before set the mode. The level power supply (V1-V62) is in OFF condition during the 8-color mode in order to select V0/V63.
DDRAM
Display Data
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B5
B4
B3
B2
B1
B0
6
6
6
Positive Polarity Resigter
PKP02 PKP12 PKP22 PKP32 PKP42 PKP52 PRP02 PRP12 VRP02 VRP12 PKP01 PKP11 PKP21 PKP31 PKP41 PKP51 PRP01 PRP11 VRP01 VRP11 PKP00 PKP10 PKP20 PKP30 PKP40 PKP50 PRP00 PRP10 VRP00 VRP10
V0
8
VRP14
VRP03 VRP13
Grayscale Amplifier
2 levels
ON/OFF Control
ON/OFF Control
ON/OFF Control
Negative Polarity Resigter
PKN02 PKN12 PKN22 PKN32 PKN42 PKN52 PRN02 PRN12 VRN02 VRN12 PKN01 PKN11 PKN21 PKN31 PKN41 PKN51 PRN01 PRN11 VRN01 VRN11 PKN00 PKN10 PKN20 PKN30 PKN40 PKN50 PRN00 PRN10 VRN00 vRN10
V63
LCD Driver IC
Display
VRN14
VRN03 VRN13
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7.11 Power Supply Circuit
7.11.1 External Configuration of Power Supply Circuit
Capacitor
Capacity 1uF 0.1F~1.0uF Recommended voltage 6V 25V Capacitor No. C1, C2, C3, C4, C7, CA, CB, CC, CD, CE C5, C6, C8, C9
Shot-Key Diode
Feature VF<0.4V/20mA at 25 , VR>=30V Connect Pin. GND-VGL VCI-VGH VCI-DVDDH
Variable resistor
Feature >200K Connect Pin. VcomR
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8. Internal Instruction (Command) Data Bus and Register
MSB R/W Command read/write Internal OSC Resistor selection Driver Output Set LCD Driving Wave Form Set Entry Mode Display Control 1 Display Control 2 Display Control 3 Frame Cycle Set Power Control 1 Power Control 2 Power Control 3 Power Control 4 Fuse Set W W W W W W W W W W R RAM Address Set Write Data to DDRAM Gamma Control Set W R W W W W W W W W W W Gate Scan Set Vertical Scroll Set 1st Screen Drive Set 2nd Screen Drive Set Horizontal RAM Address Position Vertical RAM Address Position W 1 0 VEA[7:0] VSA[7:0] 45h W 1 0 HEA[7:0] HSA[7:0] 44h W 1 SE2[7:0] SS2[7:0] 43h W W W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Write Data to DDRAM WD[17:0], depend on the selected interface 22h Read Data from DDRAM RD[17:0], depend on the selected interface PKP1[2:0] PKP3[2:0] PKP5[2:0] PRP1[2:0] PKN1[2:0] PKN3[2:0] PKN5[2:0] PRN1[2:0] VRP1[4:0] VRN1[4:0] SS1[7:0] 42h VL[7:0] PKP0[2:0] PKP2[2:0] PKP4[2:0] PRP0[2:0] PKN0[2:0] PKN2[2:0] PKN4[2:0] PRN0[2:0] VRP0[3:0] VRN0[3:0] SCN[4:0] 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 40h 41h W 1 1 1 1 1 1 1 1 1 1 1 1 0 0 NO[1:0] DFM[1:0] BGR PT[1:0] SDT[1:0] SAP[2:0] DC2[2:0] VCOMG
LSB D11 * 0 D10 * 0 D9 * 0 D8 * 1 D7 0 0 * 0 * 1 * RAJ[2:0] 0 0 0 * D6 D5 D4 D3 D2 I[6:0] * * OSCPWR * * OSCON * 00h D1 D0 Code
R/S 0 0 1 1
D15 * 0
D14 * 1
D13 * 1
D12 * 1
W R W R
W W
1 1
-
-
-
-
-
SM
GS B/C
SS EOR
-
-
-
NL[4:0] NW[5:0]
01h 02h
FLD[1:0]
-
-
-
SPT
-
-
ID[1] GON PTG[1:0] DIV[2:0] AP[2:0] DC0[2:0]
ID[0] DTE -
AM
ACGO
D[1]
D[0]
03h 07h 08h
VLE[1:0] FP[3:0] EQ[1:0] BT[2:0] DC1[2:0] VDV[4:0] -
CL BP[3:0]
REV
-
-
ISC[3:0] RTN[3:0] PON DK SLP VC[2:0] VRH[3:0] VCMF[1:0] FSA[4:0] STB
09h 0Bh 10h 11h 12h 13h 15h
-
-
-
-
-
-
VCM[4:0] 0
FSAEN
0
0
0
0
0
0
0 AD[15:0]
*
*
*
*
*
* 21h
SE1[7:0]
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Note
Instruction Data Bus and External Data Bus mapping EXT: External Data Bus CMD: Internal Instruction Data Bus
18,16 Bits Interface
EXT CMD D17 D15 16 D14 D15 D13 D14 D12 D13 D11 D12 D10 D11 D9 D10 D8 D9 -D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 --
"--": don't care
9,8 Bits Interface First Transfer
EXT CMD D17 D15 D16 D14 D15 D13 D14 D12 D13 D11 D12 D10 D11 D9 D10 D8 D9 -D8 -D7 -D6 -D5 -D4 -D3 -D2 -D1 -D0 --
"--": don't care
Second Transfer
EXT CMD D17 D7 D16 D6 D15 D5 D14 D4 D13 D3 D12 D2 D11 D1 D10 D0 D9 -D8 -D7 -D6 -D5 -D4 -D3 -D2 -D1 -D0 --
"--": don't care
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Command read/write (IR)
R/W W INI RS 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 0 D6 D5 D4 D3 I[6:0] 0 0 0 0 D2 D1 D0
Write: The index instruction specifies the RAM control indexes (R00h to R45h). It sets the register number from 0000000 to 1111111 in binary form. Don't use the register or instruction bits to which the index is not assigned. Read: Read instruction reads the internal status of the ST7712. (LADDER[7:0]: Indicate the position of raster-row driving liquid crystal; I[6:0]: Read value of the Instruction Register.) INI: The internal state after resetting of ST7712
Internal Register selection (00h)
W/R W R INI RS 1 1 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 0 D6 0 D5 1 0 1 D4 D3 RAJ[2:0] 0 0 0 0 D2 D1 OSCPWR * 0 D0 OSCON * 0
Write
RAJ[2:0]: When OSCON=1 and OSCPWR=0, the internal resistor for OSC can be adjusted by setting RAJ[2:0].
RAJ1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 RAJ2 0 1 0 1 0 1 0 1 RAJ3 internal resistor for OSC 350K 280K 250K 220K 190K (Default value) 170K 160K 120K Unit(KHz)
OSCPWR: Select Internal or external OSC power and OSC. When OSCPWR=0, use the internal OSC power and resistor When OSCPWR=1, use the external OSC power and resistor OSCON: Turn on or turn off the OSC. When OSCON=0, OSC OFF When OSCON=1, OSC ON
Read
D15-D4: Identify the ST7712. The data read from D15-D4 can tell ST7712 from the other ICs. D15-D12 fixed to "0111" (07h) D11-D8 fixed to "0001" (01h) D7-D4 fixed to "0010" (02h) D1 and D0 are read as the status of OSCPWR and OSCON.
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Command Read flow chart 18bits and 16 bits interface mode read flow chart
9bit, 8bit and SPI interface mode read flow chart
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Driver Output Set (01h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 SM 0 D9 GS 0 D8 SS 0 D7 D6 D5 1 1 D4 D3 D2 NL[4:0] 1 0 1 D1 D0
SM: Set the scan order by the gate driver.
SM 0 1 Scan order interlaced gate order cascaded gate order
SM 0
GS 0
Scan direction G0,G1,G2,G3..... G129,G130,G131
0
1
G0 G2
G1 G3
G131,G130,G129.... G4,G3,G2,G1
TFT Panel
G129 G131
G128 G130
G0
G130
G131
G1
ST7712
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1 0 G0,G2,G4,G6.... G128,G130 G1,G3,G5,G7.... G129,G131
1
1
G0,G2,G4,G6.... G128,G130 G1,G3,G5,G7.... G129,G131
Note: When the cascade function is used (SM=1) with 128X128 resolution, the even side layout of gate line must be starting from G0,G2,...,G130 and the odd side layout of gate line must be starting from G1,G3,..G123. Example: TFT-Panel layout with 128X128 resolution.
GS: Set the shift direction of outputs from the gate driver. When GS=0, G0 shift to G131; when GS=1, G131 shift to G0. GS Shift direction 0 Low to High Gate order (G0 to G131) 1 High to Low Gate order (G131 to G0)
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SS: Set the shift direction of outputs from the source driver. When SS=0, S0 shift t0 S395; when SS=1, S395 shift to S0. SS Shift direction Note 0 Source shift from S0 to S395 SS=0, BGR=0 RGB
1 Source shift from S395 to S0 SS=1, BGR=0 BGR
SS=0, BGR=1 BGR SS=1. BGR=1 RGB
Note1: When source output channels and Gate output channels of IC are not total occupied, some lines will no display when GS or SS register is changed.
NL[4:0]: Set the number of LCD raster-rows. The DDRAM address mapping is not affected by this setting. Raster-rows number= NL*4+16. Note: The setting value should be larger than the panel size. NL4 NL3 NL2 NL1 NL0 LCD Display size Gate line in raster-rows use 0 0 0 0 0 16 396x16 dots G0~G15 0 0 0 0 1 20 396x20 dots G0~G19 0 0 0 1 0 24 396x24 dots G0~G23 0 0 0 1 1 28 396x28 dots G0~G27 0 0 1 0 0 32 396x32 dots G0~G31 0 0 1 0 1 36 396x36 dots G0~G35 : : : : : : : : 1 1 0 1 1 124 396x124 dots G0~G123 1 1 1 0 0 128 396x128 dots G0~G127 1 1 1 0 1 132 396x132 dots G0~G131 1 1 1 1 0 Setting Disable 1 1 1 1 1 Note: A front porch (FP) and a back porch period (BP) will be inserted as a blank period area before/after driving all gate lines.
LCD Driving Wave Form Set (02h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 B/C 0 D8 EOR 0 D7 D6 0 0 0 D5 D4 D3 D2 D1 D0
FLD[1:0] 0 1
NW[5:0] 0 0 0
FLD [1:0]: Set the number of fields during n-field interlaced drive. FLD[1:0] Number of Fields
0 0 1 1 0 1 0 1 1 field VS when B/C=0 VCOMAC fix at VCOMH B/C=1 VCOMAC fix at VCOML 1 field 2 field 3 field
B/C: When B/C =0, enter the VCOMAC frame inversion mode, means where alternations occur every frame while driving liquid crystal. When B/C=1, enter the VCOMAC n-raster-rows inversion mode. EOR: When BC=1 and EOR = 1, the odd/even frame-select signals and the n-raster-row reversed signals are EOR (Exclusive-OR) for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the number of the LCD drive raster-row and the n raster-row. When BP and FP setting value is even, set EOR=1 to gain better display quality.
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NW[5:0]: Set the number "n" of n-raster-rows VCOMAC inversion (when B/C="1")
The number of "n"= NW[5:0]+1 (NW[5:0] sets from 0 to 63)
Entry Mode (03h)
W/R W INI RS 1 D15 D14 D13 D12 BGR 0 D11 D10 D9 D8 D7 D6 D5 ID[1] 1 D4 ID[0] 1 D3 AM 0 D2 ACGO 0 D1 D0 -
DFM[1:0] 1 0
DFM[1:0]: Decide the data format for the RAM write data transmission. DFM1 DFM0 Number of Colors 0 0 Setting disable 0 1 Setting disable 1 0 262K color 1 1 65K color BGR: When BGR=0, the data order write to DDRAM is R, G, B. When BGR=1, the data write to DDRAM order reverse from R, G, B to B, G, R. RGB SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 ... SEG395 0 R G B R G B R G ... B 1 B G R B G R B G ... R
Note: When BGR is used (BGR=1), the read out data of red-pixel and blue-pixel should be exchanged to gain the correct data or the data of red-pixel and blue-pixel are not correct.
ID[1]: When ID[1]=1, the Address Counter incremented by 1 horizontally. When ID[1]=0, Address Counter horizontal decremented by 1 horizontally. ID[0]: When ID[0]=1, the Address Counter incremented by 1 vertically. When ID[0]=0, Address Counter horizontal decremented by 1 vertically.
Note: The increment/decrement setting of the address counter by ID[1] and ID[0] is performed independently for the upper (AD15-8) and lower (AD7-0) addresses. The AM bit sets the direction of moving through the addresses when the DDRAM is written.
AM: When AM = "0", the address counter is updated in the horizontal direction after data are written to DDRAM. When AM = "1", the address counter is updated in the vertical direction after data are written to DDRAM.
When the window address is specified, data are written to the DDRAM area specified by the window address in the manner specified with ID[1] ,ID[0] ,and AM settings.
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ID[1]=0; ID[0]=0 H: decrement V: decrement AM=0 Horizontal
(00h,00h) (00h,00h) (00h,00h) (00h,00h)
ID[1]=0; ID[0]=1 H: increment V: increment
ID[1]=1; ID[0]=0 H: decrement V: increment
ID[1]=1; ID[0]=1 H: increment V: increment
(83h,83h)
(83h,83h) (00h,00h) (00h,00h)
(83h,83h) (00h,00h)
(83h,83h)
AM=1 Vertical
(00h,00h)
(83h,83h)
(83h,83h)
(83h,83h)
(83h,83h)
Note: When changing the setting of ID[1-0] value, please set the RAM address set command(21h) again. Example: Panel resolution is 132X132 AM=0, ID[1-0]=00, RAM address set command (21h) is 83h,83h
ACGO: Decide the Address Counter will update after data are written to the DDRAM automatically or not. When ACGO=0, AC updates after data are written to the DDRAM area. When ACGO=1, AC doesn't change (keep on the AD value which be set) after data are written to or read from DDRAM area.
ACGO 0 1 AC status AC update AC keep AD value
Power up (04h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 UP 0 D0 0 0
UP Help analog circuit stability of IC when IC turn on moment to avoid abnormal display. After analog voltage stable, must turn off this function. UP 0 1 UP status Turn OFF Turn ON
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Display Control 1 (07h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 SPT 0 D7 D6 D5 GON 0 D4 DTE 0 D3 CL 0 D2 REV 1 D1 D[1] 0 D0 D[0] 0
PT[1:0] 0 0
VLE[1:0] 0 0
PT[1:0]: Decide the source output voltage in the non-display area when entry the partial display mode. PT[1:0] Positive Polarity Negative Polarity 0 0 V63 V0 0 1 V63 V0 1 0 GND GND 1 1 Hi-Z Hi-Z VLE[1:0]: When VLE[0] = 1, the first screen is scrolled in the vertical direction; when VLE[1] = 1, the second screen is scrolled in the vertical direction. Note: The first and second screens can't be scrolled at the same time. VLE[1] VLE[0] Scree2 Screen1 0 0 Stationary Stationary 0 1 Stationary Scrolled 1 0 Scrolled Stationary 1 1 Setting disabled SPT: When SPT=0, liquid crystal is one screen. When SPT = 1, liquid crystal is driven with 2 split screens. GON: When GON = 0, the gate-on level is VGH, and the gate-off level is GND. When GOC=1, the gate-on level is VGH, and the gate-off level is VGL. DTE: When DTE=0, the DISPTMG is fixed to GND, and when DTE=1, the DISPTMG is output operation. CL: When CL = 1, entry the 8-color display mode. RAM data format have to redefine before writing into IC RAM to avoid abnormal display. CL=0: 262K color; CL=1: 8 color 8 color mode data format: Pattern REV=1 REV=0 Black 000000,000000,000000 111111,111111,111111 White 111111,111111,111111 000000,000000,000000 Red 111111,000000,000000 000000,111111,111111 Green 000000,111111,000000 111111,000000,111111 Blue 000000,000000,111111 111111,111111,000000 Yellow 111111,111111,000000 000000,000000,111111 Magenta 111111,000000,111111 000000,1111111,000000 Cyan 000000,111111,111111 111111,000000,000000 REV: When REV=0, the display is normal in display area; when REV = 1, the display entries reverse mode in display area. Normally white or normally black panels can be controlled by the grayscale level inversion without changing the data.
REV DDRAM Data 0 000000 : 111111 000000 : 111111 V63 : V0 V0 : V63 V0 : V63 V63 : V0 Positive Polarity Negative Polarity
1
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D[1]/ D[0]: Display is on when D[1] = 1 and off when D[1] = 0. When off, the display data remains in the DDRAM, and can be displayed instantly by setting D[1] = 1. When D[1]= 0, the display is off with the entire source outputs set to the GND level. By this function, ST7712 can control the charging current for the LCD with AC driving. Control the display on/off while control GON and DTE. When D[1]=0 and D[0]=1, the internal display of ST7712 performed although the display is off. When D[1]=0 and D[0]=0, the internal display operation halts and the display is off.
D[1] D[0] Source Output Internal operation Gate-Driver Control Signals 0 0 GND Halt Halt 0 1 GND Operate Operate 1 0 Non-lit display Operate Operate 1 1 Display Operate Operate Note: 1. Write from the microcomputer to the DDRAM is independent from D[1] and D[0]. 2. In sleep and standby mode, D[1]=0 D[0]=0. However, the register contents of D[1] and D[0] are not modified.
Display Control 2 (08h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 1 0 D6 D5 D4 D3 D2 D1 D0
FP[3:0] 1 0
BP[3:0] 0 0 1 0
FP[3:0]/ BP[3:0]: Setting the blank display area (the front porch and the back porch). The front porch is placed at the beginning of the display and the back porch is placed at the end of the display. FP[3:0] and BP[3:0] bits specify the number of raster-rows for the front and back porches respectively. When making this setting, make sure that BP + FP 16 raster-rows, FP 1 raster-rows, and BP 0 raster-rows. FP3 FP2 FP1 FP0 Number of lines for the Front Porch 0 0 0 0 Setting disable 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 Setting disable BP3 BP2 BP1 BP0 Number of lines for the Back Porch 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10
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1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 11 12 13 14 Setting disable
Display Control 3 (09h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTG[1:0] 0 0 0
ISC[3:0] 0 0 0
PTG[1:0]: Set the mode of scanning gate lines when non-display area is driven. Gate output in non display area 0 0 Normal scan 0 1 Fixed VGL 1 0 Interval scan 1 1 Setting disable ISC[3:0]: Set the cycle to scan gate lines. When PTG bits set the scan mode in the non-display area to the interval scan mode, the scan cycle is always odd number of frames, and polarity inversion is applied each timing when gate lines are scanned.
Note: 1. When PTG is set to "Normal Scan", the source output in non-display area should be set to "V63-V0" (PT=0 or 1) to avoid flicker effect. 2. When PTG is set to "Fixed VGL" and "Interval Scan", the source output in non-display area should be set to "GND" (PT=2) to avoid data leakage.
PTG[1]
PTG[0]
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ISC3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ISC2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ISC1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ISC0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Scan cycle (Scan cycle=ISC*2+1) 0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Example: Interval scan: Scan cycle=3.
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Frame Cycle Set (0Bh)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NO[1:0] 0 0
SDT[1:0] 0 0
EQ[1:0] 0 0
EQPW[1:0] 0 0
DIV[2:0] 0 0 0
RTN[3:0] 0 0 0 0
NO[1:0]: Set the non-overlap width of gate output
NO1 0 0 1 1 NO0 0 1 0 1 Non-overlap width 0 clocks 4 clocks 6 clocks 8 clocks
Note: The amount of non-overlap width is defined from the falling edge of the CL1.
CL1 1 H period 1 H period
Gn Non-overlap period
Gn+1
SDT[1:0]: Specify the delay time for the source output from the falling edge of the gate output.
SDT1 0 0 1 1 SDT0 0 1 0 1 Delay time for source output disable 2 clocks 3 clocks 4 clocks
Note: The delay time for the source output is measured from the falling edge of the CL1.
1 H period CL1 1 H period
M
Gn
Sn Source output delay
EQ[1:0]: EQ period is sustained for the number of clock cycle which is set on EQ[1:0]. EQ1 EQ0 0 0 No EQ 0 1 1 clocks 1 0 2 clocks 1 1 3 clocks
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EQPW[1:0]: Decide the source output voltage in the equalized area. EQPW[1:0] Positive Polarity Negative Polarity 0 0 V0 V63 0 1 V63 V0 1 0 GND GND 1 1 Hi-Z Hi-Z DIV[2:0]: Set the division ratio of clocks for internal operations. Internal operations are in synchronization with the clock, the frequency of which is divided according to the DIV[2:0] setting. Frame frequency can be adjusted in combination with the adjustment of 1H period (RTN [3:0]). When changing the number of drive raster-rows, adjust the frame frequency too. For details, see "Frame Frequency Adjustment Function".
DIV2 0 0 0 0 1 1 1 1 DIV1 0 0 1 1 0 0 1 1 DIV0 0 1 0 1 0 1 0 1 Division Ratio 1 2 4 8 3 5 6 7 Internal Operating Clock Frequency fosc/1 fosc/2 fosc/4 fosc/8 fosc/3 fosc/5 fosc/6 fosc/7
RTN[3:0]: Set the clock cycles per raster-row
RTN3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RTN2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RTN1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RTN0 0 1 0 1 0 1 0 1 0 1 0 1 0: 1 0 1 clock cycles per raster-row 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks
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Power Control 1 (10h)
W/R W INI RS 1 D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 0 D2 DK 1 D1 SLP 0 D0 STB 0
SAP[2:0] 1 0
BT[2:0] 0 0
AP[2:0] 1 0
SAP[2:0]: The amount of fixed current from the fixed current source in the operational amplifier for the source driver is adjusted. When the amount of fixed current is large, LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During non-display operation, set SAP[2:0]="000" to halt the operational amplifier to reduce the current consumption.
SAP2 0 0 0 0 1 1 1 1 SAP1 0 0 1 1 0 0 1 1 SAP0 0 1 0 1 0 1 0 1 OP current Halt Setting Disabled 0.63 0.73 1 1.25 1.42 Setting Disabled
BT[2:0]: Change the step-up scale of the step-up circuit by VCI1. Adjust the scale according to the voltage in use. Smaller scale consumes lesser current. Adjust the frequency considering the display quality and the current consumption.
BT2 BT1 BT0 VLOUT1 output (DDVDH) Vci x 2 VLOUT4 output (VCL) Vci x -1 VLOUT2 output (VGH) Vci1 x 6 VLOUT3 output (VGL) Vci1x-5 Capacitor connection pins DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22,
0
0
0
0
0
1
Vci1 x 6
Vci1x -4
0
1
0
Vci1 x 6
Vci1x-3
0
1
1
Vci1x5
Vci1x-5
1
0
0
Vci1x5
Vci1x-4
1
0
1
Vci1x5
Vci1x -3
1
1
0
Vci1x4
Vci1x -4
1
1
1
Vci1x4
Vci1x-3
Note 1) The capacitor connection pins are step-up capacitors which are necessary for DDVDH, VCL, VGH, VGL voltages. Note 2) Each of following voltages should be within the following range: DDVDH = 6.0 V (Max.), VCL = - 3.3V (Min.), VGH = 16.5 V (Max.), VGL = -15V (Min.)
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AP[2:0]: Adjust the amount of constant current from the constant current source of operational amplifier for the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. During non-display operation, set AP[2:0]= "000" to halt the operational amplifier and step-up circuits to reduce current consumption.
AP2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 AP1 0 1 0 1 0 1 0 1 AP0 Output OP Driver current adjustment Setting Disabled Setting Disabled 0.54 0.75 1 1.26 1.53 1.74
DK: Control the operation of the step-up circuit 1. When turning on the power supply, stop the startup of VLOUT1 for a moment, and wait for an enough time until VLOUT2 is stabilized before starting up VLOUT1.
DK 0 1 Operation of step-up circuit 1 Operation Halt
SLP: When SLP = 1, the sleep mode is entered.
SLP 0 1 Status Operation Sleep only OSC is working
In the sleep mode, internal display operation is halted except the R-C oscillator to reduce current consumption. Only power control instructions (BT[2:0], DC[2:0], AP[2:0], SLP, STB, VC[2:0], VRH[4:0], VCOMG, VDV[4:0], and VCM[4:0] bits) are executed during the sleep mode. No change is made to the DDRAM data or instructions during the sleep mode, and the DDRAM data and the instructions are retained.
STB: When STB = 1, the standby mode is entered.
STB Status 0 Operation 1 Stand-by OSC is halted In the standby mode, display operation is completely halted, and all internal operations including the internal R-C oscillator and reception of external clock pulse, are halted. For details, see the "Standby Mode" section. Only instructions to release from the standby mode (STB = 0) and to start oscillation are accepted during the standby mode. DDRAM data and instructions are susceptible to destruction during the standby mode and require resetting after release from the standby mode.
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Power Control 2 (11h)
W/R W INI RS 1 D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 0 D2 D1 D0
DC2[2:0] 1 0
DC1[2:0] 1 0
DC0[2:0] 1 0
VC[2:0] 1 0 0
DC2[2:0]: Set the frequency of the step-up circuit 4. Note: The higher frequency causes the better drive capacity of step-up circuit as well as the display quality, but it causes the higher current consumption, too.
DC22 0 0 0 0 1 1 1 1
DC21 0 0 1 1 0 0 1 1
DC20 0 1 0 1 0 1 0 1
frequency of the step-up circuit 4 fosc/4 fosc/8 fosc/16 fosc/32 fosc/64 fosc/128 Setting disable Setting disable
DC1[2:0]: Set the frequency of the step-up circuit 2. : Note: The higher frequency causes the better drive capacity of step-up circuit as well as the display quality, but it causes the higher current consumption, too.
DC12 DC11 DC10 frequency of the step-up circuit 2 0 0 0 fosc/4 0 0 1 fosc/8 0 1 0 fosc/16 0 1 1 fosc/32 1 0 0 fosc/64 1 0 1 fosc/128 1 1 0 Setting disable 1 1 1 Setting disable DC0[2:0]: Set the frequency of the step-up circuit 1. : Note: The higher frequency causes the better drive capacity of step-up circuit as well as the display quality, but it causes the higher current consumption, too. DC02 0 0 0 0 1
1 1 1
DC01 0 0 1 1 0
0 1 1
DC00 0 1 0 1 0
1 0 1
frequency of the step-up circuit 1 fosc/2 fosc/4 fosc/8 fosc/16 fosc/32 fosc/64 Setting disable Setting disable
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VC[2:0]: Adjust the reference voltage for VREG1OUT, VciOUT voltages to the optimum ratio of VCI.
VC2 0 0 0 0 1 1 1 1 VC1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 0 1 0 1 REGP reference voltage VCI 0.92xVCI 0.87xVCI 0.83xVCI 0.76xVCI 0.73xVCI Hi-Z VCIRIN (2.4V regulated)
Power Control 3 (12h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 PON 0 0 D3 D2 D1 D0 VRH[3:0] 0 0 0
PON: Start operation of Step 2 and Step 4 circuit. PON = "0": stop operation of Step 2 and Step 4 circuit; PON ="1": start operation the operation of Step 2 and Step 4circuit. VRH[3:0]: Set the ratio of VREG1OUT voltage (the reference voltage for VCOM and grayscale voltage). REGP voltage is amplified by 1.33 ~ 2.79 times. VRH3 VRH2 VRH1 VRH0 VREG1OUT ratio by REGP 0 0 0 0 1.33 0 0 0 1 1.45 0 0 1 0 1.55 0 0 1 1 1.66 0 1 0 0 1.76 0 1 0 1 1.81 0 1 1 0 1.86 0 1 1 1 Halt 1 0 0 0 1.91 1 0 0 1 1.96 1 0 1 0 2.01 1 0 1 1 2.07 1 1 0 0 2.13 1 1 0 1 2.17 1 1 1 0 2.22 1 1 1 1 Halt
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Power Control 4 (13h)
W/R W INI RS 1 D15 D14 D13 VCOMG 0 D12 D11 D10 D9 D8 D7 0 0 0 D6 D5 D4 D3 D2 D1 D0
VDV[4:0] 0 0
VCM[4:0] 0 0 0 0 0
VCMF[1:0] 0 0
VCOMG: When VCOMG = 1, VCOML can output the negative voltage. VCOMG = 1 is valid when PON = 1. When VCOMG = 0, VCOML will fixed to GND. VDV[4:0]: Set the Vcom alternating amplitude during Vcom alternating drive. The amplitude can be selected among VREG1OUT x discrete times from 0.6 to 1.2. When VCOMG = 0, this setting is invalid.
VDV4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 VDV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 VDV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VDV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VDV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcom amplitude VREG1OUTx0.6 VREG1OUTx0.61 VREG1OUTx0.62 VREG1OUTx0.63 VREG1OUTx0.64 VREG1OUTx0.65 VREG1OUTx0.66 VREG1OUTx0.67 VREG1OUTx0.68 VREG1OUTx0.70 VREG1OUTx0.71 VREG1OUTx0.72 VREG1OUTx0.74 VREG1OUTx0.75 VREG1OUTx0.77 VREG1OUT x0.78 VREG1OUT x0.8 VREG1OUT x0.81 VREG1OUT x0.83 VREG1OUT x0.85 VREG1OUT x0.87 VREG1OUT x0.89 VREG1OUT x0.91 VREG1OUT x0.93 VREG1OUT x0.96 VREG1OUT x0.98 VREG1OUT x1.04 VREG1OUT x1.07
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1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 VREG1OUT x1.10 VREG1OUT x 1.13 VREG1OUTx1.16
VCM[4:0]: Set the VcomH voltage (a high-level voltage at the Vcom alternating drive). These bits amplify the VcomH voltage 0.4 to 0.98 times the VREG1 voltage. When VCM[4:0] = "11111" and VCMF[1:0] = "11", the adjustment of the internal volume stops, and VcomH can be adjusted from VcomR by an external resistor.
VCM4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VCM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VCM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VCM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VcomH VREG1OUTx0.98 VREG1OUTx0.96 VREG1OUTx0.94 VREG1OUTx0.92 VREG1OUTx0.90 VREG1OUTx0.88 VREG1OUTx0.86 VREG1OUTx0.84 VREG1OUTx0.82 VREG1OUTx0.80 VREG1OUTx0.78 VREG1OUTx0.76 VREG1OUTx0.74 VREG1OUTx0.72 VREG1OUTx0.70 VREG1OUTx0.68 VREG1OUT x0.66 VREG1OUT x0.64 VREG1OUT x0.62 VREG1OUT x0.60 VREG1OUT x0.58 VREG1OUT x0.56 VREG1OUT x0.54 VREG1OUT x0.52 VREG1OUT x0.50 VREG1OUT x0.48 VREG1OUT x0.46 VREG1OUT x0.44 VREG1OUT x0.42 VREG1OUT x0.40
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1 1 1 1 1 1 1 1 0 1 VREG1OUT x 0.38 Halt internal volume. Adjust with a variable external resistor from VcomR. (Note: VCMF[1:0]="11")
VCMF[1:0]: To fine tune the VCOM value. After adjust the VCOM by setting VCM[4:0], the fine tuning of each scale of VCM[4:0] can be achieved by setting VCMF[1:0]. Each scale of VCM[4:0] can be divided into 4 . When use VcomR as VcomH reference voltage VCMF[1:0], should be "11"
Fuse Set (15h)
W/R W R INI RS 1 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 FSAEN * 0 * 1 * 0 D4 D3 D2 FSA[4:0] * 0 * 0 * 0 D1 D0
Write
FSAEN: When FSAEN=0, the VcomH Reference voltage is shifted by setting up the fuse pins of FUSA[4:0]. When FSAEN=1, the VcomH Reference voltage is shifted by setting up the registers of FSA[4:0]. FSA[4:0]: FSA[4:0] are the fuse registers for VcomH reference voltage offset. The more accurate VcomH voltage can be adjusted by setting FSA[4:0].
Read
D[5]: Read the stats of FSAEN D[4:0]: Read the status of FUSA[4:0] or FSA[4:0]. When FSAEN=0, the read-out value of D[4:0] is the setting value of FUSA[4:0] When FSAEN=1, the read-out value of D[4:0] is the setting value of FSA[4:0]
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Fuse set flow chart Trim Fuse: 1. Connect ground to pin VSSF of ST7712, 2. Vci pad should be connected with FUSA4 to FUSA0 sequentially with a voltage pulse. The width of pulse should be longer than 100ms, the voltage level should be higher than 10V (Current limitation of power supply should be smaller 200mA to avoid damaging fuse circuit) and current level should be higher than 50mA. 3. Each fuse pins within FUSA0 to FUSA3 corresponding to the registers FSA0 to FSA3 won't be trimmed when each register value is 0. THe fuse pin FUSA4 won't be trimmed as the logic value of corresponding register FSA4 is 1. 4. Set register FSAN to 0 in command 15H to enable the VCOM adjustment controlled by fuse pins FUSA[4:0].
Example: FSA4 Initial Adjusted by Register Need to Trim 1 0 Yes FSA3 0 0 No FSA2 0 1 Yes FSA1 0 1 Yes FSA0 0 0 No
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Connect diagram
RAM Address Set (21h)
W/R W INI RS 1 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AD[15:0] 0 0 0 0 0 0 0 0 0
AD[15:0]: Set DDRAM addresses to the address counter (AC). The AC is automatically updated according to the AM and ID bit settings after the DDRAM data is written. This allows consecutive accesses without resetting address. Once the DDRAM data is read, the AC is not automatically updated. DDRAM address setting is not allowed in the standby mode. Make sure that the address is set within the specified window address.
Bitmap data for Source S0 SS1 .. S130 "0000"H "0001"H .. "0082"H "0100"H "0101"H .. "0182"H "0200"H "0201"H .. "0282"H : : .. : "8000"H "8001"H .. "8082"H "8100"H "8101"H .. "8182"H "8200"H "8201"H .. "8282"H "8300"H "8301"H .. "8382"H
DDRAM Setting G0 G1 G2 : G128 G129 G130 G131
S131 "0083"H "0183"H "0283"H : "8083"H "8183"H "8283"H "8383"H
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Bitmap data for Gate
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Write Data to DDRAM (22h)
W/R RS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W R
1 1
WD[17:0] RD[17:0]
Write
WD[17:0]: Write 18-bit data to the DDRAM (depend on the selected interface). This data selects the grayscale level. After a write, the address is automatically updated according to AM and ID bit settings. During the standby mode, the DDRAM cannot be accessed.
Write Data Flow chart
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Read
RD[17:0]: Read 18-bit data from the DDRAM (depend on the selected interface). When the data is read to the MCU, the first-word read immediately after the DDRAM address setting is latched from the DDRAM to the internal read-data latch. The data on the data bus (DB17-DB0) becomes invalid and the second-word read is normal.
18bit and 16bit interface mode Read flow chart 9bit, 8bit and SPI interface mode Read flow chart
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Gamma Control Set (30h~39h)
W/R W INI W INI W INI W INI W INI W INI W INI W INI W INI W INI 1 1 1 1 1 1 1 1 1 RS 1 D15 D14 D13 0 0 0 0 D12 D11 0 VRP1[4:0] 0 VRN1[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 D10 D9 D8 D7 0 0 0 0 0 0 0 0 D6 D5 D4 0 0 D3 0 0 0 0 0 0 0 0 D2 D1 D0
PKP1[2:0] 0 PKP3[2:0] 0 PKP5[2:0] 0 PRP1[2:0] 0 PKN1[2:0] 0 PKN3[2:0] 0 PKN5[2:0] 0 PRN1[2:0] 0
PKP0[2:0] 0 PKP2[2:0] 0 PKP4[2:0] 0 PRP0[2:0] 0 PKN0[2:0] 0 PKN2[2:0] 0 PKN4[2:0] 0 PRN0[2:0] 0 0 0 0 0 0 0 0 0
VRP0[3:0] 0 0 0
VRN0[3:0] 0 0 0
PKP5[2:0]~ PKP0[2:0]: The fine adjustment registers for positive polarity. PRP1[2:0]~ PRP0[2:0]: The gradient adjustment registers for positive polarity. PKN5[2:0]~ PKN0[2:0]: The fine adjustment registers for negative polarity. PRN1[2:0] ~PRN0[2:0]: The gradient adjustment registers for negative polarity. VRP1[4:0]~ VRP0[3:0]: The amplitude adjustment registers for positive polarity. VRN1[4:0]~ VRN0[3:0]: The amplitude adjustment registers for negative polarity.
For details, see the "Gamma Control" section.
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Gate Scan Set (40h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 0 D4 D3 D2 D1 D0
SCN[4:0] 0 0 0
SCN[4:0]: Set the scanning starting position of the gate driver.
SCN4 0 0 0 0 : 1 1 : 1 SCN3 0 0 0 0 : 0 0 : 1 SCN2 0 0 0 0 : 0 0 : 1 SCN1 0 0 1 1 : 0 0 : 1 SCN0 0 1 0 1 : 0 1 : 1 Scan start line (Start line=SCN*8) 0 G7 G15 G23 : 127 Setting disable
Note: When setting the Gate scan set instruction SCN[4:0] value, it will not output data .
Vertical Scroll Set (41h)
W/R
W
RS
1
D15
-
D14
-
D13
-
D12
-
D11
-
D10
-
D9
-
D8
-
D7
D6
D5
D4
D3
D2
D1
D0
VL[7:0] 0 0 0 0 0 0 0 0
INI
VL[7:0]: Specify scroll length at the scroll display for vertical smooth scrolling. The number of raster-rows is specified from 0 to 131. The raster-rows of the specified number are scrolled during display. When the 132nd raster-row is displayed, the scrolling display starts to fresh from the 1st raster-row. The display-start raster-row VL[7:0] is valid when VLE[0] = 1 or VLE[1] = 1. VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 Display-start Raster-row 0 0 0 0 0 0 0 0 0 raster-row 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 1 0 2 raster-row 0 0 0 0 0 0 1 1 3 raster-row : : : : : : : : : 1 0 0 0 0 0 1 0 130 raster-row 1 0 0 0 0 0 1 1 131 raster-row 1 0 0 0 0 1 0 0 Setting disable : : : : : : : : 1 1 1 1 1 1 1 1
Note: The scroll range of screen can't not over partial display screen size or it will happen abnormal display.
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1st Screen Drive Set (42h)
W/R W INI RS 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SE1[7:0] 0 0 0 0
st
SS1[7:0] 0 0 0 0 0 0 0 0 0 0 0 0
SE1[7:0]: Setting the end line of 1 screen. The liquid crystal is driven by to the gate driver of the set value. For instance, when SS1[7:0]= "03"H and SE1[7:0] = "09"H, the liquid crystal is driven from G3 to G9, and G0 to G2, and G10 thereafter are non-display drive. Ensure that 00hSS1[7:0]SE1[7:0]83h. SS1[7:0]: Setting the start line of 1 screen. The liquid crystal is driven by from the gate driver of the set value .
st
2nd Screen Drive Set (43h)
W/R W INI RS 1 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SE2[7:0] 0
nd
SS2[7:0] 0 0 0 0 0 0 0 0 0 0 0
0
SE2[7:0]: Setting the end line of 2 screen. The liquid crystal is driven by from the gate driver of the set value . nd SS2[7:0]: Setting the start line of 2 screen. The liquid crystal is driven by from the gate driver of the set value .
Note1: The second screen is driven when SPT = 1. Note2: Ensure that 00hSS1[7:0] SE1[7:0]SS2[7:0]SE2[7:0]83h.
Horizontal RAM Address Position (44h)
W/R W INI RS 1 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HEA[7:0] 0 0 0 0 0 0 0 0
HSA[7:0] 0 0 0 0 0
HEA[7:0]: Setting the end line of the window-address range in the horizontal direction by address. HSA[7:0]: Setting the Start line of the window-address range in the horizontal direction by address.
These addresses must be set before RAM write and data are written to DDRAM within the area limited by the addresses set by HSA[7:0] and HEA[7:0]. Note: Ensure that "00h" HSA[7:0]HEA[7:0]"83h
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Vertical RAM Address Position (45h)
W/R W INI RS 1 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VEA[7:0] 0 0 0 0 0 0 0 0
VSA[7:0] 0 0 0 0 0
VEA[7:0]: Setting the end line of the window-address range in the vertical direction by address. VSA[7:0]: Setting the start line of the window-address range in the vertical direction by address.
These addresses must be set before RAM write and data are written to DDRAM within the area limited by the addresses set by VSA[7:0] and VEA[7:0]. Note: Ensure that "00h" VEA[7:0]VSA[7:0]"83h"
"00h" HSA[7:0]HEA[7:0]"83h"
"00h" VSA[7:0]VEA[7:0]"83h"
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9 Instruction Setting Flow
Make the setting for each instruction according to the following sequence.
9.1 Display OFF & Display ON
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9.2 Initial Code Setting Flow chart
When turning on the power supply, follow the sequence below. The stabilization time for the oscillation circuits, step-up circuits, and operation amplifiers may vary depending on the external resistors and capacitors.
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9.3 Power Supply Setting Flow
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9.4 Sleep and Standby Sequence
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9.5 Partial Display Setting Flow
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9.6 Switch Between 262,144-color mode and 8-color mode setting flow chart
262,144 color to 8 color Display off GON=0, DTE=0,D[1:0]=0,0 8 color to 262,144 color Display off GON=0, DTE=0,D[1:0]=0,0
RAM setting
RAM setting
LCD Driving Wave Form set B/C=0
LCD Driving Wave Form set B/C=1
Power Control 1 SAP=000,BT[2:0], AP=000
Power Control 1 SAP=[2:0],BT[2:0], AP=[2:0]
CL=1
CL=0
Display on GON=1, DTE=1,D[1:0]=1,1
Display on GON=1, DTE=1,D[1:0]=1,1
Display in 8 color mode
Display in 262,144 color mode
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10. Absolute Maximum Values
Item
Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Power supply voltage (4) Power supply voltage (5) Power supply voltage (6) Power supply voltage (7) Input voltage Operating temperature Storage temperature
Symbol
Vcc Vci - GND DDVDH - GND GND -VCL DDVDH- VCL VGH - GND GND - VGL Vt Topr Tstg
Unit
V V V V V V V V
Value
-0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 7.0 -0.3 ~ -4.0 -0.3 ~ + 8.0 -0.3 ~ + 16.5 -0.3 ~ - 15 -0.3 ~ Vcc + 0.3 -40 ~ + 85 -55 ~ + 110
Notes
1, 2 1, 2 1, 2 1, 2 1 1, 2 1, 2 1 1, 3 1
C C
Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above absolute maximum values. It is also recommended to use the LSI within the electric characteristic conditions during normal operation. Exceeding the conditions may lead to malfunction of LSI and affect its credibility. Note 2) The voltage from GND. Note 3) The DC and AC characteristics of chip and wafer products are guaranteed at 85 C.
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10. Electric Characteristics
DC Characteristics (VDD = 1.8 to 3.3 V, Ta = -40 to +85C
Item Symb ol
Note 1
)
Test Condition Min Typ Max Notes
Uni t
Input high value Input low voltage (1) (OSC1 pin) Input low voltage (2) (Except OSC1 pin) Output high voltage (1) (DB0~17 pins) Output low voltage (1) (DB0~17 pins) I/O leakage current (IIOVCC+IVCC+IVCI) Current consumption during normal operation 262K mode (IIOVCC-GND+IVCC-GND+IVCIGND)
VIH VIL1
V V
VCC = 1.8 to 3.3 V VCC = 1.8 to 3.3 V
0.8 VCC 0
---
VCC 0.2 VCC
1 1
VIL2
V
Vcc=1.8V to 2.4V Vcc=2.4V to 3.3V
0 0 0.8VCC
----
0.2 VCC 0.2 VCC
1 1 1
VOH
V
VCC = 1.8 to 3.3 V, IOH = 0.1 mA
Vcc
VOL
V
VCC = 1.8 to 3.3 V, IOL = 0.1 mA
0
--
0.2 VCC
1
ILi
A
Vin = 0 to VCC
0
--
1
1
IOP1
mA
R-C oscillation=190KHZ; VCC = 2.8 V, DVDDH=5.4V, REV=1, Ta = 25 C, SAP="010",AP="010",FLD="01", BC=1, NW="00000" RAM data 0000h
1.3
1
Current consumption 8-color mode, 30-line partial (IIOVCC-GND+IVCC-GND+IVCIGND)
Iop2
A
R-C oscillation=190KHZ; VCC = 2.8 V, DVDDH=5.4V, REV=1, Ta = 25 C, SAP="010",AP="010",FLD="01", BC=1, NW="00000" RAM data 0000h
350
1
Current consumption during normal operation (Vcc-GND)
IVCC
A
R-C oscillation=190KHZ; VCC = 2.8 V, DVDDH=5.4V, REV=0, Ta = 25 C, SAP="010",AP="010",FLD="01", BC=1, NW="00000" RAM data 0000h
--
60
80
1
LCD power supply current (Vci-GND) 262,144 color display mode
IVci1
mA
R-C oscillation=190KHZ; VCC = 2.8 V, DVDDH=5.4V, REV=1, Ta = 25 C, SAP="010",AP="010",FLD="01", BC=1, NW="00000" RAM data 0000h
1.2
1
LCD power supply current (Vci-GND) 8-color mode, Ver 2.3
IVci2
A
R-C oscillation=190KHZ; VCC = 2.8 V, DVDDH=5.4V, REV=1, Ta = 25 C,
250
1
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ST7712
30-line partial
SAP="010",AP="010",FLD="01", BC=1, NW="00000" RAM data 0000h
Current consumption during standby & sleep operation (VDD-GND) Liquid Crystal Power Current (DDVDH-GND)
IST
A
Vcc = 2.8V, Ta<=50 C
--
40
100
1
ILCD
A
Vcc=2.8V, VDH=5.243V, CR Oscillation=190KHz; Ta=25 C, RAMdata:0000h, REV="0", SAP="010",AP="010", VRN[4:0]="0", PKP[52:00]="0", PRP[52:00]="0", VRN[4:0]=VRP[4:0]="0" PKP[52:00]="0", PRP[52:00]="0"
--
450
550
1
Liquid Crystal Drive Voltage (DDVDH-GND) Output Voltage deviation
VLCD
V
--
4.5
--
6.0
1
Vo
mV
Source>4.2V, Source<0.8V 0.8V--
20 12
--
1
Variation of average output voltage Gate Ron resistor Ron
mV
--
--
--
35
1
360
1
Notes to Electrical Characteristics
1. 2.
The TEST1 and TEST2 pins must be grounded (GND). The IM3/2/1/0 must be fixed at either GND or Iovcc level The output voltage difference is the difference in voltage levels output from adjacent source pins for a same grayscale. This value is for reference.
3.
The average output voltage variance is the difference in the average source output voltages of the same product. The average voltage source output voltage is measured when all output pins output the voltage for a same grayscale.
Ver 2.3
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AC Characteristics
(VDD = 1.8 to 3.3 V, Ta = -40 to +85C ) Clock Characteristics (VDD = 1.8 to 3.3 V)
Item
External clock Frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock Duty Trcp Tfcp FOSC %
Symbol
Fcp
Unit
kHz
Test Condition
Min
100
Typ
270
Max
600
Notes
VDD = 1.8 t0 3.3V
VDD = 1.8 t0 3.3V VDD = 1.8 t0 3.3V VDD = 1.8 t0 3.3V
Rf=240K VCC=3V
45 --192
50 --240
55 0.2 0.2 288
s s
kHz
Liquid crystal driver output characteristics
Item Symbol Unit Test Condition Min Typ Max
Driver output delay time
tdd
s
VDD =2.8V, VDH=5.4V,
CR oscillation ;fosc=190kHz(132 lines), Ta=25REV="0", SAP="010", AP="010", VRN[4:0]="0",VRP[4:0]="0" PKP[52:00]="0",PRP[12:00]="0" PKP[52:00]="0",PRP[12:00]="0" All pins changes at the same time from same grayscale. The time till output level reaches 35mV when VCOM polarity changes. Load resistance R=10kLoad capacity C=20pF
--
30
--
Ver 2.3
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Electrical Characteristics
1. Applies to the internal oscillator operations using external oscillation resistor Rf
OSC1 Rf OSC2
The oscillation frequency may vary depending on the capacitors for OSC1, OSC2 pins. Place OSC1 and OSC2 close to each other.
Notes:
The Rf resistor value should be based on the RC loading of panel and FPC to fine tune Rf value to apparoach the osc frequency that customer need.
Ver 2.3
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ST7712
11. TIMING CHARACTERISISTICS
conditionBare Die System Bus Read/Write Characteristics 1(For the 8080 Series MPU)
VIH VIL VIH VIL
RS
tAW8
VIH VIL VIL
tAH8
VIH
XCS
tCYC8 tCCLR,tCCLW WR,RD
VIH VIL VIH VIL
tCCHR,tCCHW tDS8 DB17 to DB0 (Write)
VIH VIL
tDH8
VIH VIL
tACC8 DB17 to DB0 (Read)
VOH VOL
tOH8
VOH VOL
Figure 11-1
(VDD =3.3V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RD Enable H pulse width (READ) tCCHR 80 ns tDH8 tCCLR 10 80 ns ns WR tAW8 tCYC8 tCCLW tCCHW tDS8 30 120 50 70 50 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
Ver 2.3
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(VDD =2.8V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RD Enable H pulse width (READ) tCCHR 80 ns tDH8 tCCLR 10 80 ns ns WR tAW8 tCYC8 tCCLW tCCHW tDS8 30 120 50 70 50 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
(VDD =1.8V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RD Enable H pulse width (READ) tCCHR 80 ns tDH8 tCCLR 10 80 ns ns WR tAW8 tCYC8 tCCLW tCCHW tDS8 30 120 50 70 50 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
Ver 2.3
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System Bus Read/Write Characteristics 1(For the 6800 Series MPU)
Figure 11-2
(VDD =3.3V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable H pulse width (WRITE) Enable L pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RW Enable H pulse width (READ) tOH6 70 ns tDH8 tACC6 10 70 ns ns E tAW8 tCYC8 tEWLW tEWHW tDS8 20 80 40 40 40 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
Ver 2.3
90/113
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ST7712
(VDD =2.8V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RW Enable H pulse width (READ) tCCHR 70 ns tDH8 tCCLR 10 70 ns ns E tAW8 tCYC8 tCCLW tCCHW tDS8 20 80 40 40 40 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
(VDD =1.8V, Ta=-40~85)
Rating Item
Address hold time RS Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) WRITE Data setup time DB0~DB17 WRITE Data hold time Enable L pulse width (READ) RW Enable H pulse width (READ) tCCHR 70 ns tDH8 tCCLR 10 70 ns ns E tAW8 tCYC8 tCCLW tCCHW tDS8 20 80 40 40 40 ns ns ns ns ns
Signal
Symbol Min
tAH8 10
Units Max
ns
Ver 2.3
91/113
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ST7712
Serial Interface (4-Line Interface)
Figure 11-3
(VDD =3.3V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time RS Address hold time Data setup time SDI Data hold time XCS-SCL time SCL L pulse width (READ) SCL H pulse width (READ) XCS tCSH tSDOS tSDOH 30 110 110 ns ns tSDH tCSS 20 20 ns tSAH tSDS 10 10 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSAS 50 20 30 20
Units Max
ns
ns
Ver 2.3
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(VDD =2.8V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time RS Address hold time Data setup time SI Data hold time CS-SCL time SCL L pulse width (READ) SCL H pulse width (READ) XCS tCSH tSDOS tSDOH 30 110 110 ns ns tSDH tCSS 20 20 ns tSAH tSDS 10 10 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSAS 50 20 30 20
Units Max
ns
ns
(VDD =1.8V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time RS Address hold time Data setup time SDI Data hold time XCS-SCL time SCL L pulse width (READ) SCL H pulse width (READ) XCS tCSH tSDOS tSDOH 30 110 110 ns ns tSDH tCSS 20 20 ns tSAH tSDS 10 10 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSAS 50 20 30 20
Units Max
ns
ns
Ver 2.3
93/113
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ST7712
Serial Interface(3-Line Interface)
Figure 11-4
(VDD =3.3V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time SDI Data hold time XCS-SCL time SCL L pulse width (READ) SCL H pulse width (READ) XCS tCSH tSDOS tSDOH 30 110 110 ns ns tSDH tCSS 20 20 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSDS 50 20 30 10
Units Max
ns
ns
(VDD =2.8V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time SDI Data hold time XCS-SCL time SCL L pulse width (READ) XCS tCSH tSDOS 30 110 ns tSDH tCSS 20 20 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSDS 50 20 30 10
Units Max
ns
ns
Ver 2.3
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2007/07/19
ST7712
SCL H pulse width (READ) tSDOH 110 ns
(VDD =1.8V, Ta=-40~85)
Rating Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time SDI Data hold time XCS-SCL time SCL L pulse width (READ) SCL H pulse width (READ) XCS tCSH tSDOS tSDOH 30 110 110 ns ns tSDH tCSS 20 20 ns SCL
Signal
Symbol Min
tSCYC tSHW tSLW tSDS 50 20 30 10
Units Max
ns
ns
Ver 2.3
95/113
2007/07/19
ST7712
Reset Timing Characteristics (Vdd = 1.8 to 3.3V)
tRW RES tR Internal status During reset Reset complete
(VDD =3.3V, Ta=-40~85)
Item
Reset low-level width tRW tR
Symbol Min
Rating
Typ Max
Units us
1
--
-1
Reset high-level width
(VDD =2.7V, Ta=-40~85)
Item
Reset low-level width tRW tR
Symbol Min
Rating
Typ Max
Units us
1
--
-1
Reset high-level width
(VDD =1.8V, Ta=-40~85)
Item
Reset low-level width tRW tR
Symbol Min
Rating
Typ Max
Units us
1
--
-1
Reset high-level width
Ver 2.3
96/113
2007/07/19
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12. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7712 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7712 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7712 Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080 Series 18bits MPUs
(2)
8080 Series 16bits MPUs
(3) 8080 Series 9 bits MPUs
Ver 2.3
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(4) 8080 Series 8 bits MPUs
(5) 6800 Series 18 bits MPUs
(6) 6800 Series 16 bits MPUs
Ver 2.3
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2007/07/19
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(7) 6800 Series 9 bits MPUs
(8) 6800 Series 8 bits MPUs
(9) Using the Serial Interface (4-line interface)
Ver 2.3
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(9) Using the Serial Interface (3-line interface)
MPU
Ver 2.3
100/113
ST7712
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ST7712
13. Application circuit
Ver 2.3
101/113
2007/07/19
ST7712
TFT Subtrate Odd lines
Interface: 8080 series-18bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
G129
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E_RD RW_WR RS
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
102/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
Interface: 8080 series-16bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 G129
10
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
103/113
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ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
Interface: 8080 series-9bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V)
G131 VCMDUMMY1 DUMMYB S394 S392
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
G129
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
VR>200K
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
104/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
Interface: 8080 series-8bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V)
G131 VCMDUMMY1 DUMMYB S394 S392
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
G129
3 C2 3 C4 3
S395 S393
3
D1
DISPLAY
VR>200K
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 10 5 5 10 10 D2 10 C7 C8 C6
G0 DUMMYD
G2
Even lines
Ver 2.3
105/113
2007/07/19
ST7712
TFT Subtrate Odd lines
Interface: 6800 series-18bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
G129
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
106/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
CA 10 CC 10 CB 10 C1
30 50 30
Interface: 6800 series-16bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 G129
VR CD
Option
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
107/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
CA 10 CC 10 CB 10 C1
30 50 30
Interface: 6800 series-9bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 G129
VR CD
Option
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
DB1 E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
108/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
Interface: 6800 series-8bits Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V)
G131 VCMDUMMY1 DUMMYB S394 S392
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
G129
3 C2 3 C4 3
S395 S393
D1 3
DISPLAY
VR>200K
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
E_RD RW_WR RS
XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 5 10 10 D2 C7 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
109/113
2007/07/19
ST7712
TFT Subtrate Odd lines
DUMMYA G3 G7 DUMMY9 open DUMMY8 open DUMMY7 open VCOM2 VCOM2 DUMMY6 open VCL VCL VLOUT4 VCOML VCOML VCOML VCOMH VCOMH VCOMH DUMMY5 open VERG1OUT VCOMR VLPWR C11+ C11+ C11+ C11+ C11C11C11C11VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VMON VGS VGS REGP open FUS4 open FUS3 open FUS2 open FUS1 open FUS0 VSSF FUSA4 FUSA3 FUSA2 FUSA1 FUSA0 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND OSC2 OSC1 VCILVL VDDO VDDO VCI VCI VCI VCI VCI VCI VCC VCC VCC VCC VCC VCC IOVCC IOVCC XRESET DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB09 IOGNDDUM2 open IOGNDDUM2 open DB08 DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 E_RD RW_WR RS SDO SDI SCL XCS FLM IOGNDDUM1 IOGNDDUM1 IM3 IM2 IM1 IM0 IOVCCDUM1 IOVCCDUM1 VGL VGL VGL VGL VLOUT3 C12C12C12C12C12+ C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ VLOUT2 VGH VGH DUMMY4 VCOM1 VCOM1 DUMMY3 DUMMY2 DUMMY1
FPC
G1 G5
10
Interface: SPI 4-Lines Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
G131 VCMDUMMY1 DUMMYB S394 S392 G129
CA 10 CC 10 CB 10 C1
30 50 30
VR CD
Option
3 C2 3 C4 3 D1 3
S395 S393
DISPLAY
3
C3
3
30 30 30
3 3 3 3 3 3
3
GND
Option
30 30 30
S198 S196
S199 S197
X Y (0,0)
10 CE Option
3
VCC
30 30 30 30 30 30 30 30 30 30
XRESET
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
RW_WR RS SDO SDI SCL XCS
3
50 50 50 50
3
3 3 10
D3 C9
S0 DUMMYC VCMDUMMY2 G128
S1
G130
C5 10
10 C6 10 5 C7 5 10 10 D2 C8
G0 DUMMYD
G2
10
Even lines
Ver 2.3
110/113
2007/07/19
ST7712
Interface: SPI 3-Lines Vcc=2.4V~3.3V Vci=2.5V~3.3V IOVCC=1.8V~3.3V 1uF(6V):C2,C3,C4,C7,CA,CB,CC,CD,CE 0.1uF(20V):C5,C6,C8,C9 Shot key diode (VF<0.4V/20mA at 25 VR>=30V) VR>200K
Ver 2.3
111/113
2007/07/19
ST7712
ST7712 Serial Specification Revision History
Version 0.0 0.2f 0.2f 0.2f 0.3a 0.3a 0.3a 0.3a 0.3a 0.3a 0.3a 0.4a 0.4a 0.4a 0.4a 0.4a 0.4b 0.4b 0.4b 0.4b 0.4b 0.5 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 Ver 2.3 Date 2004/7/26 2005/6/8 2005/6/8 2005/6/8 2005/7/7 2005/7/7 2005/7/7 2005/7/7 2005/7/7 2005/7/7 2005/7/7 2005/9/5 2005/9/5 2005/9/5 2005/9/5 2005/9/5 2005/9/26 2005/9/26 2005/9/26 2005/9/26 2005/9/26 2005/10/3 Preliminary spec. Add application notes and timing Add Alignment mark coordinate Add instruction flow chart and demo code Change GVDD to VREG1OUT Modify partial_display flow chart code Modify STB and SLP operation code form 0x0010 to 0x0001 Modify VCM and VDV register ratio table Delete EQ description when Vcom<0 abnormal display Modify application circuit and add recommend OBL resistor Add VCMDUMMY1,VCMDUMMY2/DUMMY1~DUMMY9 /DUMMYA~DUMMYD description Add switch 8-color mode to 262,144-color mode flow chart and code Add partial-display note Modify partial-display flow chart Modify DC1[2:0] and DC0[2:0] frequency Modify Trim fuse note Add 8 color mode data format table Add power up command (04H) Modify command 42H,43H set value of gate driver Modify external capacitor(C5,C6.C8,C9) of power supply circuit range 0.1uF~1.0uF Correct Partial_display flow chart Specification modify Description
2005/11/24 Modify VCM table 2005/11/24 Modify timing table and add SPI read timing 2005/11/24 Add cascade application note 2005/11/24 Modify power up command table(04H) 2005/11/24 Add BGR=1 application note 2005/11/24 Modify VOH/VOL specification table 2005/11/24 Add option test capacitance notes in Application circuit 2005/11/24 Modify internal signals of read mode 112/113 2007/07/19
ST7712
1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.1 1.1 1.2 1.2 1.2 2.0 2.0 2.1 2.1 2.1 2.2 2.3 2006/01/04 VRH table modify 2006/01/04 Modify Trim fuse current limitation specification 2006/01/04 Modify 8 color display flow chart 2006/01/04 Modify 8 color mode and partial display current specification 2006/01/04 Modify SLP and STB example code setting value 2006/1/19 2006/1/19 2006/1/19 2006/1/19 2006/5/10 2006/5/10 2006/5/10 2006/6/16 2006/6/16 2006/7/4 2006/7/4 2006/7/4 2006/7/7 2007/7/19 Modify SLP and STB flow chart Modify Initial Code Setting Flow Chart remark Add Power Supply Setting Flow Modify SLP and STB current maximum value Delete external resistor table and add application notes Disable SDT=1 colocks register value Add trim fuse connect diagram Delet example initial code setting. Please refer to application notes Modify Chip thickness 38125um 40025um and Bump heigh 173um 153um Modify Figure 7.2.1 timing chart Modify 12.The MCU interface(reference sample) Data pin defind of IC side Modify 13. Application circuit the node of C1 Modify SDO direction of Block diagram Correct I/O pad size
Ver 2.3
113/113
2007/07/19

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